Lead Free 2015

It is hard to believe that in July we will celebrate the 9th anniversary of the advent of RoHS. So the timing seemed right when I was recently asked to speak at the Boston SMTA Chapter on The Status of Lead-Free 2015: A Perspective.

An overview of the entire 75-minute presentation would be a bit long, so I am going to discuss three of the “questions” that I covered.

  1. Q: We are now almost nine years into RoHS’s ban on lead in solder. How has lead-free assembly worked out?

A: Something over $7 trillion of electronics have been produced since RoHS came into force, with no major reliability problems. One senior person, whose company has sold hundreds of millions of lead-free devices since 2001, reports no change in field reliability. The challenge that implementing lead-free assembly placed on the industry should not be minimized, however. Tens of billions of dollars were spent in the conversion. In addition, failure modes have occurred that were not common in tin-lead assembly, such as the head-in-pillow and graping defects. But assemblers have worked hard with their suppliers to make lead-free assembly close to a non-issue. Some people ask how I can say that lead-free assembly is close to a non-issue. My office is across the hall from some folks that purchase millions of dollars of electronics a year for Dartmouth. Several years ago, I asked them how they feel that electronics perform since the switch to lead-free. They answered by saying “What is lead-free?” If people that buy millions of dollars of electronics have not even heard of lead-free it can’t be a big issue.

  1. Q: In light of sourcing difficulties, is there an industry consensus regarding lead-free conversion for military, medical, aerospace etc. assemblers that will continue to be exempt?

A: The main issue is getting components with tin-lead leads, especially BGA balls. Many assemblers are reballing BGAs, which has become a mature technology, although with an added cost. As years go by and there becomes more confidence in medium to long term lead-free reliability, some exemptees may switch to lead-free. However, I think mission critical applications with 40-year reliability requirements must be extremely cautious to make the switch. There may be subtle reliability issues that may show up in 40 years, that are not found in accelerated testing. One concern is aging. Even at room temperature, solders are at over 50% of their melting temperature on the absolute scale (300K/573K = 0.52). So aging can occur at room temperature. Some research suggests that lead-free alloys may be more affected by aging than tin-lead alloys.

  1. Q: It has been said that you claim that lead-free assembly has some advantages. Can this be true?

A: Guilty as charged. Lead-free solder does not flow and spread as well as tin-lead solder. This property can result in poor hole fill in wave soldering and some other assembly challenges. However, this poor wetting and spreading means that pads can be spaced closer on a PWB without the concern of shorting as seen in the image below. Your mobile phone would likely be bigger if assembled with tin-lead solder.


Lead-free solder does not flow as well as tin-lead solder. Hence, closer pad spacings are possible.



Dr. Ron

Photo courtesy of Vahid Goudarzi.


Using the Newest Gen Arm Microcontrollers

I’ve written a few times about the new Freescale KL03 ARM Cortex M0+ microcontroller. This particular part comes only in very small packages, with the smallest being a 1.6 x 2mm WLCSP (wafer level, chip scale package) 0.4mm pitch, 20 bump BGA. That’s a mouthful — albeit a very tiny mouthful. Maybe just a toothful.

On the left, here, I’ve got a pair of them on a US postage stamp.

For us, it’s not a particularly difficult part to assembly; just a garden variety 0.4mm pitch BGA, as far as we’re concerned. We place loads of them. But, it can be a very different story for a designer. Conventional wisdom says that a PCB designer has two choices with a part like this: a very expensive PCB, or don’t use the part.

Escape routing becomes very difficult (read: expensive) at 0.4 mm pitch. This part only has six connections that need to be escaped, but that can still be a problem. You can’t fit vias between the pads to escape out the back side. You can’t put vias in the pads unless you have them filled and plated over at the board house. That’s expensive in small quantities.

This blog post series is going to examine some possible ways to use these parts with more of a standard fab, such as Sunstone Quickturn. I’ve got three different process blank PCBs, each with four different land patterns.

I’ve been asked about home reflow too, so as a bonus, I’ve done my best to duplicate hobbyist conditions for one of the board sets.

Duane Benson
“Screaming Reflowster” not sold here


Component Packages — Let’s Get Small

I’ve been on a bit of a package binge lately. First talking about metric vs. US passive sizes, and then a very tiny ARM Cortex M0 from Freescale.

The Freescale BGA part checks in at 1.6 x 2mm. That’s cool and I’m almost always in favor of making things as small as possible, but, as I wrote in my prior blog on the subject, it’s not always possible. The 0.4mm pitch BGA is problematic unless you can spend a lot of money on the raw PCBs, or will have super high volume.

All is not lost, though. You still can use a tiny ARM Cortex M0 part. Just not quite as tiny. That same part also comes in a 3 x 3mm QFN package. You lose four pins (16 vs. 20) going from the BGA to the QFN, but if you can handle that, it’s a very viable option that doesn’t require any exotic circuit board technologies.

A few years ago QFNs were scary, but not so much any more. I’ve designed a few of them in using Eagle CAD. Just be sure to pay attention to the footprint. A 6 mil trace is more than small enough for a 0.5mm pitch QFN.

Duane Benson
Strive at all times to bend, fold, spindle and mutilate


0.4mm Pitch BGA is Awesome

I recently had a conversation with a friend about 0.4mm pitch BGAs. The specific part is the FreescaleFreescaleKL03KL03 ARM Coretex-M0+ microcontroller in a 1.6mm x 2mm, 04.mm pitch package. That’s a 20-ball wafer scale BGA form factor.

I don’t have an actual part to photograph next to a grain of sand, but trust me (or don’t), it’s really small.

Ti 0.44 pitch dimensionsThe challenge, and the reason I suggested a QFN form factor instead, is the costs involved. If you have the extra budget money for more expensive PCBs, then go ahead and use this form factor. You probably won’t be able to use this package in cost-constrained situations.

The simple reason is that you can’t escape route the inner six pins without using super small vias between pads, or in pads and filled and plated over. The page on the left is from a Ti doc, but any variations in geometry will be minor.

You can see that you can’t put a trace between the pads. Maybe a 2 mil trace, but maybe not. There just isn’t much room. The recommended method is to put microvias in the pads and have them filled and plated over at the board fab house. Never put a via in a micro BGA pad unless it’s filled, plated over, and flat.

Duane Benson
There are more things in heaven and earth, Horatio,
Than are dreamt of in your philosophy.
But open vias in pads aren’t one of them


More Beagle CAD Paws

Continuing on from my last post

As I said, I do everything I can to avoid reusing the package footprint when adding the the parts library in Eagle CAD. The schematic symbol can be a different story though. It still takes a lot of caution, but it’s less risky (in my opinion) than reusing the package footprint.

Eagle v.  6 made some improvements in the way copy and paste works. It’s still a little different from your typical word processor, but it’s not that difficult.

Eagle footprint menu bar 3 buttonsBut before I get to that, I want to mention one item that caused me a fair amount of confusion early on. And that’s the way all of this fits together. There are three buttons you will need to worry about. From left to right in the green oval are; the device, the package footprint, and the schematic symbol. In my last post, I pointed out the package footprint and today I’m talking about the schematic symbol.

Really, you only build the footprint and the schematic symbol. Then you connect the two up to create the devices. And, you can build the footprint or schematic symbol in either order, but you have to have them both before the last step (the icon in the green oval with four little AND gates).

If you’re using a chip that comes in a couple of different packages (e.g., DIP28, SOIC28, TSSOP28) you most likely only need to make one schematic symbol. You can make the multiple footprints and connect them up in the device section as different variants of the same part.

There are a few exceptions though. Sometimes QFN, QFP or BGA parts will have a few extra pins. In those cases, it’s generally better to create a different schematic symbol.

Duane Benson
This solder paste stencil glows blue when goblins are around


How Not to Trick Your BGA Friends

Continuing with yesterday’s theme, I have a couple examples that should have been fine, but due to issues at the board house, improper storage or contamination, ended up very much not fine.

What is wrongBehind door number one, we have an OSP finish that will make you very unhappy. That’s “Organic Solderability Preservatives” in long hand. I’ve also heard it called “Organic Surface Preservative”, but close enough. It is a nice flay surface which is good for BGAs. Years ago, it had a reputation for being poor quality, “cheap”, but newer formulas seem to work pretty good in both leaded and lead free. In this case, the darker pads were likely contaminated in some way – either at the board fab house or subsequently in handling.

Siver migration problemNext is the worst example of surface degradation I’ve ever seen. Yes, it’s an extreme outlier case, but this is where a silver board can go if it wasn’t built with the best quality control, was stored too long, was exposed to polluted air or other contamination and had bad luck. This board probably has all of those issues, but any one alone can be problematic. Silver board especially should be stored in a cool dark place; preferably sealed in the original packaging.

Duane Benson
OSP can also mean Oregon State Patrol, but they don’t care about BGAs. Just safe driving.


Let’s Get Small – 0.3mm Pitch BGA

I recently got an email from Practical Components about its new 0.3mm pitch evaluation board and dummy 0.3mm pitch BGA. Now, we’ve been assembling 0.5mm and 0.4mm pitch BGAs for years. Those sizes are kind of not really anything special anymore. We’ve even been putting together PoP (package-on-package) for a couple of years. But we’ve yet to see anything smaller.

Shrinking BGA pitchJust looking at the numbers, 0.3 may not look all that much smaller than 0.4, but that’s 25% down. Thinking of it in those terms makes it much more intimidating. I haven’t found the pad dimensions yet, but just using rough estimates, a 0.003″ trace would have about 0.0015″ on either side for a between the pads trace. That’s getting pretty dangerous. Likely, you’d have to do every thing with filled and plated-over vias in the pads. (No Open Vias! Not one. Don’t do it.)

I can see a lot of good future use for this size in miniature devices; more processing power in hearing aids and embedded medical devices, for a start. I don’t know how necessary 0.3mm pitch will be for phones. They seem to have stabilized in size and the trend is more toward system in chip than it is toward more shrinking. Regardless, I would expect that in a year, we’ll be seeing mainstream parts in this form factor.

Duane Benson

Go ask Alice
I think she’ll know
How to run your escape routing



Reducing Conversion Costs

Let’s look in on Patty …

Patty was just finishing a report on work that she and Pete had performed with a team of her ACME colleagues  on reducing the head-in-pillow (HIP) defect at a plant in Minnesota. HIP can be caused by printed circuit board or BGA warping during reflow, and, occasionally, poor wetting BGA solder balls. Fortunately, this case of HIP was due to just a little warping, so replacing the solder paste with one of the new formulations that was designed to minimize HIP had done the trick. Ten thousand boards were produced with no detectable HIP defects.

As Patty wrote the last sentence in the report, she gazed out the window at the dusting of snow that had fallen. She liked living in southern New Hampshire and was thrilled with the house that she and Rob had purchased six months ago in Exeter.  She had to admit that Phillips Exeter Academy was also a draw. She hoped her 18-month-old sons, Michael and Peter, would attend high school there, when the time came.

Patty was jarred from these thoughts by the ringing of her phone. She looked at the caller ID and saw that it was Mike Madigan, the CEO of all of ACME. Her stomach tied up in a knot. Sam, her boss, had alluded to the fact that senior management wanted to make her a VP. He asked if she had any requirements to accept such an offer. She said that she wanted to stay located where she was and she wanted Pete to be on her staff. Still, she was a bit nervous about such a big change.

“Patty Coleman, how may I help you?” Patty answered.

“Coleman, this is Mike Madigan. Congratulations, you are our new VP of Technology and Productivity. You will report to me, but, since you are staying in New Hampshire, I want you to report dotted line to Sam for day-to-day things. Coleman, don’t let me down. You are the youngest VP in the history of ACME by 5 years,” Madigan said.

Patty was a little put off by his gruff manner, but had been told to expect it.

“Thank you Mr. Madigan, I’ll do my best,” Patty responded.

“I already have an assignment for you,” Madigan continued. “You have done great things by improving line uptime at many of our sites, and profitability is up everywhere, but I sense we are still missing something. Do you know why?” he asked.

“Because the correlation between profitability and uptime is not as strong as one would like?” Patty asked.

“Coleman, I’m already glad I promoted you! That is exactly my concern. Explore the situation, fix it and give me a better metric. I want all sites to use this new metric so I will know which locations to focus on. I want a status report in three weeks,” Madigan finished.

“I’ll get right on it, Mr. Madigan, and will have an update in three weeks or sooner,” Patty answered, exhilarated, but a little shaky.

“Good! Oh, and Patty, call me Mike. It’s not the 1960s, you know,” he chuckled as he hung up.

Patty hung the phone up feeling happy and stressed. She was glad to get the promotion, but knew she had to deliver.

Patty had thought about this productivity metric concern in the past. She knew where to start, she would call The Professor. She was surprised when he picked up on the first ring.

“Patty, it’s great to hear from you. How are Rob and the boys? We expect to see your sons here at Ivy University as students in 16 years,” The Professor chuckled.

After exchanging a few more pleasantries and sharing the news about her promotion, Patty got right to the point.

“Professor, I need a metric that measures total productivity in electronics assembly. Uptime is a great metric, but it doesn’t correlate one-to-one to profitability,” Patty explained.

Patty expressed her surprise that no metric for total productivity was in wide use. They discussed the issue for a few more moments and then The Professor had a recommendation. “Read the NEMI (National Electronics Manufacturing Initiative) 1998 and the iNEMI 2011  Technology Roadmaps. Focus on board assembly and I think you will find your answer,” The Professor suggested.

After a few more pleasantries, The Professor had a request.

“Patty, I am getting a little award in Washington, DC. I have room for two guests at the award presentation. I was hoping you and Rob would come,” The Professor requested.

Patty said she would check their schedules, but was sure it would work out. She was honored that he thought so much of her and Rob.

As she hung up the phone, she went to ACME’s Tech Library in search of the iNEMI roadmaps. She quickly found the 1998 NEMI Technology Roadmap, but unfortunately only a summary of the 2011 iNEMI Roadmap was available. She thought she would read the 2011 Roadmap summary first. It was overwhelmingly impressive in its coverage of technology, at the wafer, chip, component, and board levels. The thoughtful inputs of over 575 participants, from over 310 organizations, were clearly evident. All of the current and emerging technologies were presented in detail.

“What a treasure of information,” Patty thought.

But she didn’t see an answer to her question.

So she went to the “Board Assembly” section of the 1998 Roadmap and in a few minutes she saw the answer: Board Assembly Conversion Cost in cents/I/O.

“What a simple concept,” she thought.

As she studied the document it became clear that about 30% of it focused on reducing conversion costs. Conversion costs were defined as all of the cost of assembly minus materials cost. To give this metric meaning, to enable comparisons between different manufacturing sites, the total amount of conversion cost for a manufacturing site was divided by the total number of input/output (I/O) terminals (i.e,. component leads) assembled.

“This makes sense,” she thought. “You add up all of the non-material costs of assembly and divide by all of the leads you assemble. This metric shows how efficiently you assemble each lead.”

It then dawned on her that she had seen a metric like this before. She saw the notebook from The Professor’s workshop on Cost Estimating in her bookcase.  She grabbed it and flipped through it. There it was: non-material assembly cost per I/O (NMACIO).

The great mystery to her was why the folks at NEMI didn’t emphasize these types of cost performance metrics in newer roadmaps.

Best Wishes,

Dr. Ron

BGA Pads with Vias

Via eyeballs

No. This isn’t a closeup of an owl face.

There is still some debate on how best to create a land pattern for a 0.4mm pitch BGA. We recommend solder mask defined pads at that pitch. But that’s not really what this post is about. Although this land pattern uses non-solder mask defined pads which can encourage bridges. If you need to cross a river, encouraging bridges is good. If you’re trying to make a board work, they are not.

In the case of the two BGA pads shown, I really doubt you would have to worry about bridging. That’s because the solder ball would most likely be sucked off the BGA due to the capillary action of the via in the middle of the pad. You most likely wouldn’t get bridging. You most likely wouldn’t get any contact of any kind at all. This will not work.

Duane Benson
Hoot. Hoot.



What’s your favorite MCU package and why?

  • The DIP is big and easy to use. You can stick it in a breadboard (wireless or soldered), a socket or easily hand solder it. But, it tends to be more expensive and takes up more real estate.
  • SOIC is a good step down in size. It can be machine soldered. It’s big enough that most people can hand solder in a pinch. But, as an SMT, I’m not sure it has much purpose anymore. If there’s an SSOP available for the same part, why would you take the bigger SOIC package?
  • SSOP are nice and small so that, unless you are really tight on space, they’ll do just fine. They aren’t really any more difficult to layout than and SOIC. If you do need to hand-solder, this package is probably too small. Being smaller with everything else being equal, it might have more issues with heat dissipation than the bigger part or a smaller one with a heat slug under it.
  • QFP – these are just lie either an SOIC or SSOP, but with leads on four sides.
  • BGAs are really compact and and do a good job of keeping signals close to the PCB and to bypass caps. They can be a challenge to layout though. Many will require upping your layer count. The really fine pitch BGAs may require expensive PCB features such as blind or buried vias. CSP and wafer-scale BGAs can be more difficult to handle because of their small size. Breathing on them wrong can toss them around like dust.
  • QFN and DFNs are somewhat newcomers to the scene. The package can lead to some very tiny components. It’s great for signal cleanliness and the heat slug underneath can dissipate (with proper layout) a lot of heat. But, QFNs and DFNs seem to garner the most layout problems. Careful use of thermal vias is critical for maximum performance, but you either have to use expensive techniques, such as filled and plated vias, or you have to rationalize and get around some nearly mutually-exclusive requirements.

Yeah. They all have their pluses and minuses. Fortunately, with proper board design, our SMT machines can place all of the these types all day long without breaking a sweat. All the SMT designs, that is. We do hand place the DIPs. What’s your preference?

Duane Benson
All we are is BGAs in the wind