LEDs: Seeing Double

Like I do so often, I’m being a bit redundant. While I’m all for stamping out and eliminating redundancy, this is redundancy with a purpose (not a porpoise). Not long ago, in a galaxy not far away, I blogged about annoyances in surface mount diode polarity markings. You can read that here.

I’ll wait.

Messy isn’t it? Well, after reading that blog, someone asked me about dual diodes. For some reason, I can’t seem to find the page covering dual diodes in my IPC book, but that’s not the important part. What is important is the way the diodes are marked on the PC board.

We do ask for centroid data which, in theory, contains the component rotation. That would be cool except that we find that far too often, the zero degree orientation (and the rotation from that) differs from the standard. That, and there are seemingly half a dozen or so standards.

Since LEDs don’t work too well backwards, we really would like to see everything marked in a non-ambiguous way in silk screen (or in an assembly drawing if you don’t have silk screen). A “cathode bar” won’t work because it could be a bar indicating the cathode or negative. The cathode isn’t always negative, especially when looking at TVS or Zener diodes.

Mimicking the diode markation pattern printed on the part may not be secure either. Read that article I linked to right at the start of this blog. What if you put silkscreen down to match one of those LEDs but ended up buying the other one? That’s exactly what I did myself. Trust me. It just leads to disappointment and possible soldering iron induced finger burns.

So what is the answer, and why am I talking about single LEDs and TVS diodes when the blog is about dual LEDs? Well, the answer is the same. The best way to communicate the desired polarity of an LED or any kind of diode is with a mini version of the schematic symbol. It doesn’t matter if it’s a single LED, dual LED, Schottky, Zener or whatever kind of diode. The schematic symbol is the clearest way to go.

Led marking

The diode footprint has the manufacturer’s polarity marking, but I don’t care. I still put the diode schematic symbol next to it. If you don’t have room for silk screen, put it in an assembly drawing. You won’t regret it.

Duane Benson
And they called him Flipper…

http://blog.screamingcircuits.com/

Via in Pad X 8

Here’s an interesting via in pad case. On the one hand, the footprint is very symmetrical and clean looking. On the other hand, it has open vias in the pads.

At first glance, I thought this was a DIP footprint with extra long pads, but it’s not. It’s for an SMT part. Personally, I would have put mask between the pads. Looking at the rest of the board (not shown), the spacing between pads and mask is pretty wide, so there may be a good reason. I’m not sure though.

Definitely, though, I would not put the vias in the pads like that. Those open vias will cause solder to flow down to the other side of the board, make a mess there and leave the chips without sufficient solder.

Duane Benson
Sucking solder through a straw – or via

http://blog.screamingcircuits.com/

Oh MSOP, My MSOP

In the land of prototypes, sometimes “close enough” is good enough. That can save money on PCBs and assembly when a particular package version of your part is out of stock. But, it’s not universal. Sometimes you can’t go that way.

 

I’ve got an MCP78338 Li Poly charger chip. It comes in 10-DFN and 10-MSOP packages. I originally used the MSOP version on my first PCB pass. Everything worked just fine, so I re-laid out the board to be about half the area. That meant that wherever possible, passives went from 0603 to 0402 and chips went from whatever to QFN/DFN packages.

Unfortunately, the DFN package Li Poly charger seems to be out of stock with long lead times. That got me looking at my options. Option 1 would of course be to just wait. Option 2 would be to lay out the board for the MSOP part in that space. Option three is to use the “we’ll make it fit” mantra. There are no guarantees at this point, but sometimes it’s worth a try.

But… Twas not to be. If you look at the second image, you can see that the footprint of the MSOP part leads is wider than the land pads for the DFN. I suppose there are still a few really messy and potentially expensive options You could solder a small wire on to the pads, sticking out from the pads, effectively making them big enough to accommodate the chip. Very ugly, but might work. Probably too spendy, though.

Duane Benson
Carpe DFN

http://blog.screamingcircuits.com/

ValueProto from Sunstone

I think I’m done with the Geiger counter layout. Now I just need to get the thing built up to see if it works. I’m pretty sure, but you never know. I have an idea … I’ll build a prototype. And … I’ll build it in as self-serving a way as I can. How might I build a prototype in a self-serving manner?

First, I’ll use my company (and our partner Sunstone Circuits) to build it. Second, I’ll write about it here. Technically, you’re not really supposed to review your own stuff, but I really don’t get to order things very often. I know all about Sunstones’s PCB fab services, but I haven’t used their ValueProto service so I’m using this as an opportunity to do so. This PCB looks like it should work for their “ValueProto” service as well as with Screaming Circuits’ “SimpleProto” service. Small quantity, no leadless parts. Perfect for the simple and value services.

DPAK in gieger I actually made a small change since I last wrote about this design. The particular high-speed, high-voltage transistor in the original design isn’t available in an SMT package. I could have still left that one part in through-hole, but I didn’t want to so I didn’t. This is one of the reasons I understand the difficulties of parts substitution. I found two similar parts. One in a SOT-23 and the other in a larger DPAK. I really wanted the smaller package, but the specs of the DPAK part were closer. The DPAK is quite a bit bigger than the SOT-23, but it fits.

When I pulled up the layout to take this screen capture, I notices that the “Q1” label was slightly on the big pad for the DPAK. That’s not good. When I find a last minute error like that, I usually take that as a sign to go back and give everything another once-over. I’m going to do that tomorrow, so stay tuned.

Duane Benson
Same bat-channel. Same bat-time. (Different real-time though)

blog.screamingcircuits.com

Via Current Capacity

After my blog item last week, Michael asked a question about my Via in Pad Myth #5. He asked:

I have a question about vias. I have seen charts on the current carrying capacity of traces, but what about vias?

That’s a good question. I’ve heard that you first need to know the thickness of the via wall. Then, once you know that, you can calculate the trace-width equivalent for the via by using the formula for the circumference (diameter X pi ). For whatever number that gives you, compare the closest smaller trace width.

Via cross section My related questions to all of you PCB fabrication gurus out there are:

Since vias are not created in the same way as the trace plating is, can that simple formula be used? While the trace copper is laminated onto a nice smooth PCB surface, the vias are typically created by deposition of copper dust in the via and then electroplating more copper. Then the surface finish is applied to all of the exposed metal. The via walls would generally be rougher than the flat substrate surface. Does that have an impact on the current capacity of a via?

Further, since airflow will be somewhat restricted in a via relative to a surface, should the via effective width be compared to an internal trace instead of an exposed surface trace? Should it be a compromise between the two?

If you look closely at this via cross I pulled from Wikipedia, you can see that the via wall looks to be thinner that the traces. You’ll have to make sure that your board fab house can give you an accurate thickness of the via wall.

Duane Benson
If you know the via current capacity, can you calculate the past and future capacity?

http://blog.screamingcircuits.com/

0.4mm Pitch BGA Redux

I’ve written about it before, and again here.

When dealing with new technology parts, it’s really important to look up all of the manufacturer’s component information that is available. I’m going to quote from the Texas Instruments document “PCB Design Guidelines for 0.4mm Package-On-Package (PoP) Packages,” Section 10 (PDF page 8):

Industry reliability studies have revealed that NSMD-type pads are highly recommended for most 0.5mm pitch BGA applications. However, there is a problem with this approach at 0.4 mm pitch.

Real-world assembly experiments with the BeagleBoard and the OMAP35x EVM revealed a tendency for solder bridging between pads when NSMD were used. There was insufficient solder mask webbing between the pads to ward off bridging. Therefore, a SMD design was used which resulted in much better assembly yields with no solder bridging.

If you are using a 0.4 mm pitch BGA with the balls aligned in a grid (as opposed to staggered), read the design guidlines from the manufacturer before laying out the board.

In a presentation about the development of the Beagleboard, Gerald Coley, Beagleboard designer, notes that their first two runs had non soldermask defined pads, resulting in a 10% yield. After another run of PCBs where the pads on the PCB were the same size as the pads on the device and the PCB pads were soldermask defined, yields rose to 96%. And verify that your PCB house does in fact follow your instructions. Some will think they know better and will change the mask layout.

If you are still unsure or think your design will have different requirements, call an applications engineer at the component manufacturer and discuss your project and the layout.

Duane Benson
Trust but verify

http://blog.screamingcircuits.com/

AT Tiny is Tiny

ATTINY44A-MMH I just spotted a note on Twitter, from SiliconFarmer, referring to the ATtiny44A coming in a 0.45 mm pitch QFN as well as a 0.5mm pitch MLF package. (In practice, an MLF is the same as a QFN, by the way.) (Just in case you actually care, we’re on Twitter at “pcbassembly.”)

I’ve run across a number of 0.4 mm BGA packaged parts, but this is the first sub-0.5 mm QFN I’ve seen. Interesting that they have two different sizes of QFN package, one at 4 x 4 mm and the other at 3 x 3mm. If you’re that tight on space, that little 7 square mm of extra open area can make a difference.

Screaming Circuits won’t care on the assembly floor. We do plenty of 0.4 mm parts so a 0.45 isn’t anything new. The most important thing to remember is to use the right footprint. It’s easy enough to accidentally use a QFP footprint when you have a QFN (like here). I could see it being even easier to swap for the wrong footprint with this part. Doing so would be bad, most certainly. You might get one or two contacts per side on the right footprint, but that’s pretty much as good as none.

Duane Benson
It’s like Ice-9. The same, only different.

http://blog.screamingcircuits.com/