The QFN (quad flat pack, no leads) has become my favorite integrated circuit package. It’s very compact, yet is easier to use than a µBGA.

µBGAs of 0.5mm and smaller pitch become a bit more difficult and costly with more than two rows of pins. At those geometries, escape routing can involve plugged and plated vias, which add complexity and cost to the fabricated board. QFNs can be almost as small, but have all of the pins exposed around the edges, so there’s no need for escape routing.

One thing that’s important to note is that despite sharing the first two letters (Q and F), QFP and QFN footprints are not interchangeable. We do, from time to time, see boards laid out for one along with the other form packaged part.

Take a look at this PCB layout clip from the Arduino Leonardo. It has both footprints on the board. You can see how much bigger the QFP package is.

They put down both footprints because the Atmega32U4 chip used in the Leonardo sometimes has supply issues in one package or the other. This gives them the flexibility to use either without making changes on the board.

You might consider this as an option if there’s space for a QFP and you are concerned about the availability of one package variant or the other. If you do, there are some very important things to check out:

  • Make sure the pin-outs match. Some parts vary the pin-out a bit between packages or have extra pins on one or the other.
  • Make sure the extra space won’t cause noise problems. Generally, bypass caps should be as close as possible to the supply pins. This amount of extra space probably won’t be a problem when using a QFN, but in some designs it might.
  • Make sure the board won’t be in an environment where unsoldered pads will be a problem. Some harsh environments could attack the unsoldered pads. If that’s the case, consider conformal coat.

Duane Benson
We’re always being pushed and shoved by people trying to beat the clock
But we like it – it’s what we do


More Beagle CAD Paws

Continuing on from my last post

As I said, I do everything I can to avoid reusing the package footprint when adding the the parts library in Eagle CAD. The schematic symbol can be a different story though. It still takes a lot of caution, but it’s less risky (in my opinion) than reusing the package footprint.

Eagle v.  6 made some improvements in the way copy and paste works. It’s still a little different from your typical word processor, but it’s not that difficult.

Eagle footprint menu bar 3 buttonsBut before I get to that, I want to mention one item that caused me a fair amount of confusion early on. And that’s the way all of this fits together. There are three buttons you will need to worry about. From left to right in the green oval are; the device, the package footprint, and the schematic symbol. In my last post, I pointed out the package footprint and today I’m talking about the schematic symbol.

Really, you only build the footprint and the schematic symbol. Then you connect the two up to create the devices. And, you can build the footprint or schematic symbol in either order, but you have to have them both before the last step (the icon in the green oval with four little AND gates).

If you’re using a chip that comes in a couple of different packages (e.g., DIP28, SOIC28, TSSOP28) you most likely only need to make one schematic symbol. You can make the multiple footprints and connect them up in the device section as different variants of the same part.

There are a few exceptions though. Sometimes QFN, QFP or BGA parts will have a few extra pins. In those cases, it’s generally better to create a different schematic symbol.

Duane Benson
This solder paste stencil glows blue when goblins are around


Tented QFN/QFP Via-in-Pad

Below is a pretty decent example of mask-tented vias in the thermal pad of a QFP. Most manufacturers recommend no more then 100 – 125 microns wider than the via to minimize voiding and thermal insulation in cases like this. This is a reasonably inexpensive way to handle vias in the thermal pad. Sometimes though, the tents will pop open, allowing solder to wick down through the via.

The mask over the center via on the right looks a little thin, so you’d want to give it an extra look over after reflow to make sure it’s okay. (We’d do that here, of course.)

We’d rather not see this technique on really small parts because it gets difficult for the fabricator to put down the mask with enough precision. With small parts, filling and plating over the vias is the preferred technique. Well, that’s always the preferred method. It’s just more important with smaller parts and BGAs. This method is acceptable for most QFPs and larger QFNs, though.

Duane Benson
All your via are belong to us