Conductive Inks vs. Nonconductive Inks – Part II

In the first half of this column, we began a discussion of the pros and cons regarding the use of conductive inks versus nonconductive inks to fill vias. The images below show cross-sections of a via-in-pad with nonconductive ink on the left and VIP with conductive ink on the right.
 

Via-in-pad (VIP) filled with conductive ink.

Via-in-pad (VIP) filled with nonconductive ink.

Via-in-pad (VIP) filled with conductive ink.

Via-in-pad (VIP) filled with conductive ink.

 In that column, we discussed a design that required a nonconductive ink in the through-hole via and conductive ink in the blind via. Now we ask, what were the drivers behind this decision?  Why would one use two different types of inks in vias in the same PCB, and why conductive vs. nonconductive ink? The answers are actually a bit more complex.

Copper plating is one factor, as an example. For years it has been generally accepted that copper plating is not a viable substitute for ink (conductive or nonconductive) to fill a through-hole via, buried via, or blind via. It was believed that to plate a via shut and to cover the surface with copper would take “forever,” relatively speaking, if it could be done at all.

One reasoned that not only would the process of plating the via shut with copper be prohibitively time-consuming, but even if it were technically possible to fill the hole with plated copper, the unwanted consequence of plating so much copper in the hole would result in excessive “button” or surface copper height that would lead to other defects and/or reliability risks.

Blind via plated shut with copper.

Blind via plated shut with copper.

Nowadays there are several efficient processes for copper plating to fill vias; two of these are pulse and DC rectification. Some require button plating, a two-stage process; others have evolved to the point where a single-stage panel plate will fill certain via structures while depositing less material on the surface, thereby leaving a manageable surface copper thickness. In this way, one can continue to produce a high-density product without the need for a secondary ink-filling operation.

Further, there are solutions to filling micro, blind and buried vias that require no additional process time or steps; e.g., resin or B-stage fill. The consensus was that it wasn’t possible to do this reliably. While conventional prepreg (B-Stage) historically struggled to fully and consistently fill vias, there are now specialized prepregs and bonding materials specifically engineered to do just this process reliably.

One laminate company produces a series of FR-4, lead-free, polyimide, low-loss and other high-performance laminates and prepregs.  Within their product line they offer a sub-set of prepreg (B-Stage) called the VF-series (whereby VF is an abbreviation for via fill).

Via Fill (VF) prepreg product, where core and prepreg are combined to create a pure, homogeneous material package.

Via Fill (VF) prepreg product, where core and prepreg are combined to create a pure, homogeneous material package.

 

Where we have the instance of a buried via filled with one ply of VF material, the blind via is fully filled with resin, and the dielectric distance between outer foil and inner sub assembly is very uniform. In this case, the VF matches the family of core and prepreg it is combined with, so that it permits the creation of a pure homogeneous material package, eliminating the need for a hybrid material / laminate package. The VF prepreg has been engineered for enhanced rheology and filler content so that during the lamination process the blind and buried vias found in a sequential lamination sub assembly will be fully filled.

VF Prepreg is just one example of available materials designed to fill vias during the lamination process, thus eliminating the need for a secondary operation. What process and material should you use? To make the best decision, you need to understand not just what result you want to achieve, but why.

Not long ago I had an application involving a customer’s requirement of a specific brand of conductive ink to fill a small through-hole via. The assembly was a double-sided PCB on a relatively thin (0.010″ thick) PTFE/Teflon material.

The ink-filling process requires a planarization or sanding operation after the ink is cured in order to remove excess ink from the copper surface. The planarization process always includes some inherent risks and/or limitations such as:

  • Dimensional distortion of the panel of PCB material.
  • Imprecision, resulting in uneven copper thickness and poor control of circuit etching.
  • Reduced peel strength of the surface copper.

In this case, all these negative aspects of planarization were amplified because the material was a soft; thin Teflon with RA copper. This material is highly unstable to begin with and susceptible to distortion.

The PCB manufacturer struggled to meet the customer’s requirements, but excess cost, time to produce, delays, and lower yields resulting when compliant product was finally produced were a real problem, prompting further discussion with the customer.

A breakthrough occurred when we began to ask why we were using certain materials and questioned the necessity and benefit of each step in the process. We realized that the via filling; i.e., the specific material requested by the customer, was being used to prevent solder from flowing through the vias during assembly. But what else was it there for?

After critical examination, we realized:

  • That there was no need for conductivity in the filling material , let alone any reason for it to be limited to the customer’s specifically preferred ink material.
  • There was no need for a copper pad to be plated over the surface of the material or via, since nothing was being soldered on top of the via.
  • There was no need for a specific brand of ink material.
  • Alternative materials and processes could therefore be explored.

After all, we began to examine the real purpose that the via filling was intended to address, and more importantly, what it was not there for. The material had been used, all along based upon a group of assumptions that, when examined, weren’t true and did not justify the use of that specific (and costly) ink material. Its use simply could not stand up to challenging questions, such as added reliability, electrical advantages or mechanical aspects or even thermal characteristics or properties. It contributed to none of these justifying criteria.

 

Buried via fully filled with resin; note that the dielectric thickness between the outer foil and the inner subassembly is very uniform.

Buried via fully filled with resin; note that the dielectric thickness between the outer foil and the inner subassembly is very uniform.

In summary, when evaluating a new product, manufacturing process, etc.:

  • Challenge any long-held assumptions.
  • Gather information from multiple sources.
  • Qualify that what you have been told by others is really best for your needs and not skewed merely to support the choice of a specific product.

Manufacturers must talk with the designer to understand what designers really want to accomplish and why. Designers must speak with manufacturers in order to understand the intricacies of the process. Finally, as technology evolves and more innovative solutions for emerging applications or enhanced solutions for existing ones are found, cooperation and collaboration are the keys to optimizing decisions and selections.

Roy Akber

www.rushpcb.com

Super Small Via-in-Pad

Via-in-pad is an old issue that still pops up now and then. Our standard answer hasn’t changed: No open vias in pads. But one of the questions we get related to the subject is: “What if we make the vias really small?”

Logically, that makes sense. In fact, in some cases, the via is so small that it’s essentially closed. If it’s so small that it really is closed, then it’s not an open via. But look close — if it’s closed with solder, that solder may melt during reflow leading to an open via.

The images here show some pretty small vias. I believe they’re 0.3mm in diameter.

In the first picture, on the left, it appears that the vias are open. They aren’t though. This board (an unstuffed Beagleboard) uses solder mask on the back side of the PCB to close off the vias, as shown in the image on the right.

Our recommended method (see more detail here and here) is to plug the via with copper or epoxy and have it plated over at the board fabricator. Next, we’d recommend via caps on the component side. Finally, capping the back side with solder mask, like this example can work, but it comes with the risk of voids. The via caps and also pop open, leading to an open via.

Duane Benson
No more open vias-in-pad, I mean it!
Anybody want a peanit?

http://blog.screamingcircuits.com/

Will a Via Fit Between?

I don’t know that it would be accurate to say that BGAs have ever been easy, but with 0.4mm pitch being common and 0.3mm pitch showing up, some of the older size, like a WHOLE millimeter pitch seem 0.5mm pitch padspositively spacious. With 1mm and larger ball pitch, putting a via between the pads (not in the pads) is a no-brainer.

IPC-7095B classifies 0.8mm and smaller pitch as fine-pitch. It really starts to get complicated at around that point. For example, take a 0.5mm pitch BGA. Since we’re looking to put a via between the pads, the diagonal pitch is the critical measurement. In this case, it’s 0.71mm (17 mil). It might immediately seem like that’s plenty of room for a 6 mil via, but upon closer examination, not so much.

0.5mm pitch pads viasIPC states that a 0.5mm pitch BGA will have a nominal pad diameter of 0.3 mm. It should be a non-soldermask defined pad, which will add about 0.07 mm to the pad diameter. That gives 0.44 mm total pad diameter. The radius is 0.22 mm (8 mil). Take that out of the 0.35 mm (14 mil) you have to work with and you’re not left with much space.

If your fab house can do 3 mil trace and space, you will end up with enough room for a 0.06mm (5 mil) via, including annular ring. That’s not much space. Most designers, at that point, will seriously consider putting the via in the land pad and having it filled and plated over. You can’t leave the via open or un plated.

Duane Benson
All was in chaos, ’till Euclid arose and made order

http://blog.screamingcircuits.com/

Via in Pad X 8

Here’s an interesting via in pad case. On the one hand, the footprint is very symmetrical and clean looking. On the other hand, it has open vias in the pads.

At first glance, I thought this was a DIP footprint with extra long pads, but it’s not. It’s for an SMT part. Personally, I would have put mask between the pads. Looking at the rest of the board (not shown), the spacing between pads and mask is pretty wide, so there may be a good reason. I’m not sure though.

Definitely, though, I would not put the vias in the pads like that. Those open vias will cause solder to flow down to the other side of the board, make a mess there and leave the chips without sufficient solder.

Duane Benson
Sucking solder through a straw – or via

http://blog.screamingcircuits.com/

How Not to Trick Your BGA Friends

Continuing with yesterday’s theme, I have a couple examples that should have been fine, but due to issues at the board house, improper storage or contamination, ended up very much not fine.

What is wrongBehind door number one, we have an OSP finish that will make you very unhappy. That’s “Organic Solderability Preservatives” in long hand. I’ve also heard it called “Organic Surface Preservative”, but close enough. It is a nice flay surface which is good for BGAs. Years ago, it had a reputation for being poor quality, “cheap”, but newer formulas seem to work pretty good in both leaded and lead free. In this case, the darker pads were likely contaminated in some way – either at the board fab house or subsequently in handling.

Siver migration problemNext is the worst example of surface degradation I’ve ever seen. Yes, it’s an extreme outlier case, but this is where a silver board can go if it wasn’t built with the best quality control, was stored too long, was exposed to polluted air or other contamination and had bad luck. This board probably has all of those issues, but any one alone can be problematic. Silver board especially should be stored in a cool dark place; preferably sealed in the original packaging.

Duane Benson
OSP can also mean Oregon State Patrol, but they don’t care about BGAs. Just safe driving.

http://blog.screamingcircuits.com/

BGA Pads with Vias

Via eyeballs

No. This isn’t a closeup of an owl face.

There is still some debate on how best to create a land pattern for a 0.4mm pitch BGA. We recommend solder mask defined pads at that pitch. But that’s not really what this post is about. Although this land pattern uses non-solder mask defined pads which can encourage bridges. If you need to cross a river, encouraging bridges is good. If you’re trying to make a board work, they are not.

In the case of the two BGA pads shown, I really doubt you would have to worry about bridging. That’s because the solder ball would most likely be sucked off the BGA due to the capillary action of the via in the middle of the pad. You most likely wouldn’t get bridging. You most likely wouldn’t get any contact of any kind at all. This will not work.

Duane Benson
Hoot. Hoot.

http://blog.screamingcircuits.com/

Small Open Vias

Pad parts change and so do vias. Our standard policy here is that open vias in pads are bad. We from time to time recommend ways to plug them. Generally, you have several options. Like this post shows. However, with vias in the pads of really small parts, those solder mask options will probably not work. Solder mask generally isn’t put down with enough precision to cover holes on tiny pads, and further, the solder mask would probably mess with the clearance. On the left is an example of a small QFP with open vias in the pads. Those are some small vias.

So, if solder mask isn’t going to work, what QFN center void open vias will? Filling and plating over them. That’s what will work. You really only have two choices: fill and plate, or live with a bunch of voids under the part and solder slopped on the bottom side of the PCB.

Here on the right are two illustrations representing the issue. In the top half of the image on the right, I’m representing the vias with copper plugs and plated over at the board fab house. As with all parts of this sort, there may still be tiny voids. IPC and the manufacturer will have guidelines on the maximum allowable voiding. On the bottom, you see what happens with the vias left open. You get two problems: big voids and solder on the underside of the PCB.

Certainly there are some applications where this doesn’t matter. That’s why there is a second choice: “Live with a bunch of voids and slopped solder.” If you can’t live with voids and solder slop, you have to bite the bullet and pay the extra for a PCB with filled vias. Board houses that do this have a variety of materials to use including copper, electrically conductive epoxy and thermal conductive epoxy.

Duane Benson
Please sir, may I have some more voids?
No! No voids for you!

http://blog.screamingcircuits.com/

Via Current Capacity

After my blog item last week, Michael asked a question about my Via in Pad Myth #5. He asked:

I have a question about vias. I have seen charts on the current carrying capacity of traces, but what about vias?

That’s a good question. I’ve heard that you first need to know the thickness of the via wall. Then, once you know that, you can calculate the trace-width equivalent for the via by using the formula for the circumference (diameter X pi ). For whatever number that gives you, compare the closest smaller trace width.

Via cross section My related questions to all of you PCB fabrication gurus out there are:

Since vias are not created in the same way as the trace plating is, can that simple formula be used? While the trace copper is laminated onto a nice smooth PCB surface, the vias are typically created by deposition of copper dust in the via and then electroplating more copper. Then the surface finish is applied to all of the exposed metal. The via walls would generally be rougher than the flat substrate surface. Does that have an impact on the current capacity of a via?

Further, since airflow will be somewhat restricted in a via relative to a surface, should the via effective width be compared to an internal trace instead of an exposed surface trace? Should it be a compromise between the two?

If you look closely at this via cross I pulled from Wikipedia, you can see that the via wall looks to be thinner that the traces. You’ll have to make sure that your board fab house can give you an accurate thickness of the via wall.

Duane Benson
If you know the via current capacity, can you calculate the past and future capacity?

http://blog.screamingcircuits.com/

Random Via-In-Pad Myth #5

Myth #5: When you need thermal vias, more is better, bigger is better

Hmmm. Logically, this would seem to be the case. There are limits though; especially if you want a reliably assembled product. Older parts with heat slugs easily accessible for bolting on heat sinks didn’t have this issue. Just bolt on a piece of metal and maybe blow a fan across it. It’s different with a lot of the new, Padinvia smaller surface mount packages. Many have a heat slug on the bottom, which requires carefully placed thermal vias to a copper pad on the underside of the board.

An extreme case of flooding the land with vias can be seen in this illustration here on Padinvia_alt the left. In terms of assembly, you can hack this together for a prototype, but it’ll never fly in a production environment.It would be much better to use fewer smaller vias and have the center land covered with solder mask except where the metal on the chip is exposed, as in the illustration on the right.

Duane Benson
Place one carrot seed in each via and cover it with planting soil

http://blog.screamingcircuits.com/

Little Chippy Challenges

And “chippy,” in this context, refers to chip caps and any other tiny two-connector components. When considering surface mount, most people think of the many-connector parts, like BGAs and QFNs as the challenging components. That’s mostly true. However, the little passives can be big bears too if not treated properly.

Two part tombstone You could have tombstoning problems. This can be caused by unequal sized pads, unequal sized traces going to the pads or inequality in copper plane in a different layer. A big part on one side can cause tombstoning too — the big part’s thermal mass may slow the solder paste melt on one side of the part, leading to tombstoning.H Skewed passive via in pad

Via-in-pad is still a problem too. Open vias can lead to unreliable connections, tombstoning or crooked  parts.

Soldermask tombstoning for blog Solder mask can cause problems too. Too thick a solder mask can prevent the part from reaching the solder and can cause tombstoning. Too think a solder mask can also interfere with outgassing in the reflow oven which can cause solder ball splatter. (A = okay, B = not okay).

Duane Benson
It just goes to show you…
It’s always something.

http://blog.screamingcircuits.com/