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Friday, 28 September 2012 14:56

Component Assembly

“High-Reliability Component Attachment Process for <5µm Placement Accuracy”
Author: Donald J. Beck; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: As complex microelectronic packaging designs and components mature, improved placement accuracy becomes more important. High-accuracy placement has been an ongoing theme in the commercial assembly arena for several years. For example, some phononic designs require better than 2µm precision placement for optimum performance. Military and aerospace companies routinely evaluate higher precision requirements, although this has been traditionally accomplished using semi automatic bonder equipment. A manual or semiautomatic process is adequate and often perceived as essential for prototyping; however, semiautomatic processes are not practical for higher volume production. Aside from their slower speed, application performance relies on how well the technician can target the die since these systems mainly require manual alignment. This paper presents a process solution for automating sub-5µm component attach using real-world experiences. (IMAPS, September 2012)


“Additive Manufacturing of Fine Lines and Embedded Electronics for Use in Chip Packaging and Microelectronic Systems”
Author: Scott Lauer; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: Additive manufacturing techniques, the application of layer manufacturing, vary from incumbent technologies in that they only add material to build the device, and are an alternative to subtractive technologies such as lithography that globally coat layers, and then etch-away unrequired materials. Here we discuss an additive technology that performs material evaporation through shadow masks. This process has shown significant potential for the fabrication of chip packaging, microelectronic devices and circuitry; specifically, high-density interposers, fine conductor lines and embedded components such as capacitors, resistors and transistors. It has shown to be compatible with a number of rigid and flexible substrates and deposition materials. Examples of devices and lines manufactured by this technique are discussed, and preliminary test data presented with experimentation shown with line/space resolution of 15/30µm and better. (IMAPS, September 2012)

Printed Electronics

“Development of Silver Nanoparticle Ink for Printed Electronics”
Author: Yiliang Wu
Abstract: Printed/flexible electronics has attracted extensive research interest, because printing technologies such as noncontact and drop-on-demand inkjet printing promise dramatic reduction of fabrication costs. Therefore, printable conductors with high conductivity would be critical for low-cost printed electronics. Earlier work on printable conductors was focused on organic materials such as polyaniline and PEDOT doped with PSS. Besides their potential thermal and electrical instabilities, these materials generally have very low conductivity (less than 10 S/cm). In view of printability, conductivity and electrical stability, metal such as gold or silver derived from solution-deposited precursor compositions would be ideal. In the past decade, Xerox has been exploring the use of silver complex and silver nanoparticles as conductor precursor composition for printed electronics. This paper reviews research in the development of silver nanoparticles that can be sintered at low temperature (<120˚C) for high conductivity (>10000 S/cm) silver nanoparticle ink formations that exhibit surface-energy independent printability and self-assembly characteristics for defect-free printing. (IMAPS, September 2012)

Solder Materials

“Optimization of Ag Composition in Cu Pillar Bumps with Sn-xAg Solders”
Author: Moon Gi Cho, Ph.D.
Abstract: In this study, the optimum level of Ag composition in Cu pillar bump with Sn-xAg solder (<50µm in diameter) was investigated to suppress the large plate growth of Ag3Sn IMCs during reflow. In general, Ag atoms in the Sn-Ag solders react to Sn atoms, and form Ag3Sn intermetallic compounds (IMCs) in the solder matrix. Undesirably, pro-eutectic Ag3Sn IMCs grow rapidly within the liquid phase during cooling, and form large plate-like shapes. Since the undercooling of Sn-Ag solders increases with a decrease of solder ball size to less than 100um, the Ag3Sn IMCs are more prone to become largely plate-like in small solder bumps. Actually, in Cu pillar bumps with under-50µm Sn-Ag solders, the large plate-like growth of Ag3Sn was observed on the top surface of solder bumps, even though the Ag composition is less than 3.0 wt% in the solders, such as 2.3 or 2.5 wt%. The large plate-like Ag3Sn causes the noise of bump height inspection and potentially interrupts the wetting of solders on Cu pads during flip chip boning. Through the dynamic scanning calorimeter (DSC) results and the thermodynamic calculations, the optimized Ag composition in under-50µm Sn-xAg solder was suggested, and the large plate-like growth of Ag3Sn was effectively reduced in the suggested Ag composition. Another way to supress the large plate growth of Ag3Sn IMCs, such as cooling rate and reflow profile, was also reported. (IMAPS, September 2012)

Last Updated on Monday, 01 October 2012 13:42


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