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Written by Mike Buetow   
Tuesday, 01 January 2013 19:50

LEDs
“Understanding Power LED Lifetime Analysis”

Author: Philips Lumileds Lighting
Abstract: When designing LED-based lighting systems, engineers need to understand LED lumen maintenance and mortality in similar terms to those used when designing with conventional light sources. However, comparable data have been nearly impossible to find. In addition, designers need extra information to predict the lifetime of LEDs under a variety of operating conditions. A number of techniques to predict LED lifetimes have been proposed, but have not been sufficient to generate the clear and unambiguous data that lighting engineers can use easily. A new tool from Philips simplifies the process, allowing full flexibility in design options. This one tool provides information for making decisions about product lifetimes, driver constraints, number of LEDs required, and thermal management. (Company white paper)

Signal Integrity

“Bandwidth Tests Reveal Shrinking Eye Diagrams and Signal Integrity Problems”

Authors: Tim Caffee and Eric Johnson; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: Each new generation of a high-speed bus typically runs at a higher signal frequency, but this decreases the margin for error on the bus, making it more sensitive to disruptions from jitter, inter-symbol interference (ISI), crosstalk and other factors. To avoid potential problems on high-speed buses like DDR3, PCI Express, Intel QPI, Serial ATA, USB and others, bus performance must be validated during each phase of a system’s lifecycle, including design/development, manufacturing and as an installed system in the field. Unfortunately, effectively and economically validating the signal integrity on a high-speed bus has become more difficult, as the limitations of legacy probe-based test equipment such as oscilloscopes have become more obvious in recent years. Non-intrusive software-driven test methods based on embedded instrumentation are providing alternative validation solutions that are more cost-effective and deliver observed signal integrity data. (Company white paper, November 2012)

Solder Joint Reliability

“The Role of Pd in Sn-Ag-Cu Solder Interconnect Mechanical Shock Performance”

Authors: Tae-Kyu Lee, Ph.D., Bite Zhou, Thomas R. Bieler, Chien-Fu Tseng and Jeng-Gong Duh; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: The mechanical stability of solder joints with Pd added to SnAgCu alloy with different aging conditions was investigated in a high-G level shock environment. A test vehicle with three different strain and shock level conditions in one board was used to identify the joint stability and failure modes. The results revealed that Pd provided stability at the package-side interface with an overall shock performance improvement of over 65% compared with the SnAgCu alloy without Pd. A dependency on the pad structure was also identified. However, the strengthening mechanism was only observed in the non-solder mask-defined pad design, whereas the solder mask-defined pad design boards showed no improvement in shock performance with Pd-added solders. The effects of Sn grain orientation on shock performance, interconnect stability, and crack propagation path with and without Pd are discussed. SAC 305 + Pd solder joints showed more grain refinements, recrystallization, and especially mechanical twin deformation during the shock test, which provides a partial explanation for the ability of SAC 305 + Pd to absorb more shock-induced energy through active deformation compared with SAC 305. (Journal of Electronic Materials, December 2012)

“A Mechanistically Justified Model for Life of SnAgCu Solder Joints in Thermal Cycling”

Authors: Peter Borgesen, Ph.D., Linlin Yang, Awni Qasaimeh, Babak Arfaei, Liang Yin, Michael Meilunas, and Martin Anselm; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
Abstract: We have shown the life of a SAC solder joint in a typical BGA or CSP assembly in thermal cycling to scale with the time to completion of a network of high angle grain boundaries across the high strain region of the joint. This provides for a scientifically credible materials science-based model. In-depth studies did, however, show this to require significant temperature variations. Isothermal cycling may also lead to recrystallization, albeit at a much lower level depending on alloy, processes, and cycling parameters, but a quantitative model would need to be completely different. The question therefore arises as to how large a cycling temperature range is required for our model to apply. We present results indicating that repeated cycling between 20˚ and 60˚C should be sufficient; i.e., the model should permit extrapolation of accelerated test results to realistic service conditions. Many practical applications involve a combination of thermal excursions and mechanical cycling, and there is little doubt that thermal cycling-induced recrystallization will tend to lead to much faster crack growth through the solder in subsequent vibration, etc. (SMTA Pan Pac Symposium, January 2013)

This column provides abstracts from recent industry conferences and company white papers. Our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.

Last Updated on Thursday, 03 January 2013 12:08
 

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