Bridging Technology between 3D Conventional Stacking and TSV 3D Stacking Print E-mail
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Written by Belgacem Haba, Ph.D.   
Monday, 04 March 2013 12:49

A new wirebond PoP achieves nearly 1000 interconnects at 200µm pitch. 

New generations of thin notebook PCs such as the ultrabook are changing the way memory is used in portable electronics. The traditional SO DIMM is far too big and bulky to consider for these slimmed down PCs. In an effort to minimize the profile of the electronics assembly within the ultrabook product, manufacturers have resorted to soldering the memory directly on the circuit board.

The 16 single-die SDRAM packages on the ultrabook PCB are arranged in two rows of eight. The two-row 16-package memory configuration requires a rather complex interconnect scheme. Such complexity forces adoption of higher density circuit board technology.

Three conventional package configurations are currently in wide use for stacking the high-performance SDRAM (the opposing face, top face-up, bottom face-down; staggered stack RDL modified for edge bond; and the face-up, RDL modified for edge bond, Figure 1). All these configurations suffer from long connections between die pads and the package ball-out.



Two new multi-die DRAM package technology families are designed to solve specific system integration problems of growing importance in the industry. The first (Figure 2), called the Dual Face Down package, is for high-density and high-performance DIMM applications. Designed to optimize PCB layout, high-speed signal integrity and thermal performance, these dual die packages are made using standard face-down process.

The second (Figure 3), called the DIMM-in-a-Package memory device, accommodates four devices in a single component (Quad Face Down), and is specifically targeted to the new ultra-slim form-factor notebooks such as ultrabooks and tablets. Using a common ball-out scheme optimized for efficient PCB layouts on low-cost through-board via PCB technology, this same ball-out accommodates DDR3x, DDR4x and LPDDR3 devices.



Common to both solutions is the use of existing high-volume wire-bond-based face-down window-BGA DRAM assembly infrastructure. No new capital equipment is required for the assembly operations. No re-distribution layer (RDL) is required, and using common wire-bond BGA assembly, the unique structures offer single-pass line assembly.

Both families offer low profile due to the face-down structure. The face-down die orientation minimizes wire-bond length and avoids the need for thick encapsulation above the die, in contrast with face-up wire-bonding. The result is a dual-die package or quad-die package less than 1mm thick. The thin profile coupled with the die not being stacked directly atop one another offers thermal advantages (Table 1) in addition to the short electrical pathway and cost advantages.

[Ed.: To enlarge the figure, right-click on it, then click View Image, then left-click on the figure.]

DFD technology. Unlike traditional stacked-die DDPs, the DFD features separated DQ signals. The construction uses a variant of the high-volume window-BGA face-down package; a live die and a spacer die are mounted facing the substrate, and a second bonding window is added. The second memory die is stacked above the second bonding window in a shingle-like configuration. The result is a 104-ball 11.5 x 11.5 x 1mm package with 0.8 x 0.8mm ball pitch. Detailed manufacturing cost models show that the DFD costs 1.8x the cost of a single die package (SDP), translating to the cost per die actually being lower than for an SDP.

One key design feature of the DFD is the placement of the Command/Address (CA) signals in the center of the package. This solves the well-known cross-tie stub problem associated with standard single, double and quad die packages used on double-sided assemblies by decreasing the distance the cross tie stubs must be routed in the breakout region.

Another feature of the DFD is the ability to route the CA global bus in a single layer in a standard DIMM PCB process. This avoids layer-to-layer timing skew that impacts operating frequency.

High-performance quadrank RDIMMs and Hypercloud DIMMs have been manufactured and demonstrated using the DFD technology. Quadrank RDIMMs have been shown to operate reliably at 1600MT/s DDR3 rates using two Quadrank RDIMMs/channel. Single quadrank DFD-based RDIMMs have been demonstrated at 1866MT/s.

DIMM-in-a-Package. Ultra-slim notebook and tablet devices have largely been turning to solder-down single-die packaged memory and expensive HDI buildup PCB technology.  The form factor of the shrinking vertical dimensions no longer accommodates SODIMMs.

The DIMM-in-a-Package memory device has the functionality of an SODIMM (Figure 4), including an optional SPD/TSE in a single BGA, and is configurable as a single x64 or a dual channel x32 memory system in a package. The package is a 407-ball BGA using 0.8mm pitch and is 17.5 x 22.5 x 1mm. This technology features a common compatible ball-out that supports DDR3x, DDR4x and LPDDR3.



The packages using this common ball-out can be constructed using a variety of methods, including four-die structures using face-down window BGA assembly methods. This leads to a very efficient manufacturing flow; all the die are placed in a single operation and from the same wafer region, and all are wire-bonded in a single operation offering the same strips/hour assembly throughput on the same machinery as standard single-die packaging. This is the method used for building high-volume DDR3 and DDR4 versions of the novel packages, as well as the center-bonded x16 LPDDR3 version. The x32 periphery-bonded LPDDR3 versions are assembled in a two-die face-up wire-bonded configuration featuring one-pass die placement and one-pass wire-bonding as for the four-die face-down versions. The fact that within the same package the die all came from the same region of the wafer has demonstrated great binning yield. Detailed cost models indicate the QFD assembly costs 3.8x the cost of an SDP to manufacture. Again, on a per-die basis this is less than for an SDP and 2.4 times less than the QDP (Table 1).

For the system OEM and ODM the benefits are numerous. A key design goal was efficient PCB layout using a standard low-cost Type 3 PCB. Additionally, when using the second-generation ultrabook CPU that offers co-support of LPDDR3 and DDR3, a single low-cost Type 3 PCB can be designed supporting either type of memory. This greatly reduces the cost of design.

Using previous generation layout guidelines, a 40% reduction in area was attained by migrating to a 12-layer Type 4 design made using single-die packages to a low-cost Type 3 PCB using the novel package devices.

The novel package is not limited to solder-down memory applications. Using board-to-board connectors, a dual-channel module can be constructed that is the same XY size as an SODIMM but sits no higher than 3.5mm above the lower PCB. Using double-sided assembly, a 16-die dual-rank dual-channel module can be constructed.

Package-on-package stacking. Current PoP modules have limited data I/O (~32-64), and a new technology is needed to meet the high I/O (128-512) requirements. The processor-memory bottleneck must be addressed through very wide I/O for high bandwidth while consuming low power. Bond Via Array (BVATM) PoP offers bandwidth communications with wide I/O, low power memory chips using conventional wire-bond technology and existing materials and infrastructure.

Figure 5 illustrates the Bond Via Array (BVA) wire-bond array interconnect concept. The main feature is that the BVA interconnects (freestanding wirebonds) bridge the top surface of the bottom package to the bottom surface of the package mounted on top. 



The mature wire-bonding technology offers very fine-pitch, and freestanding wires are formed using proprietary processes on conventional wirebond equipment. The wirebonds can be fine pitch, and can extend in length to any desired value, thus achieving high aspect ratio (height-to-diameter ratio greater than 10).

The I/O capabilities are tabulated in Table 2. For a given 14 x 14mm package and assuming a 1mm peripheral width for I/O, up to 1440 interconnects can be formed at 0.2mm pitch. These numbers of I/O are enough to meet future wide I/O memory requirements.

A daisy-chain prototype of 432 I/O BVA PoP test vehicle was designed and fabricated that measured 14 x 14mm with two perimeter rows of copper wires at 0.24mm pitch with a wire diameter of 50µm and a height of 0.4mm. This test vehicle has an interconnect aspect ratio (height/diameter) of 8 and pitch ratio (height/pitch) of 1.7. These conditions exceed by far any existing PoP technology.

The vehicle consists of stacking a memory package over a logic package with BVA interconnects. The top (memory) package is similar to current memory packages, including high I/O BGA. The bottom package has the logic device in a flip-chip format, with the BVA wires around the periphery. The molding with wires is applied differently. Finally, stacking is done using conventional surface mount technology (SMT) with the condition that the top memory package has fine-pitch BGA. The four manufacturing process steps are described below.

The freestanding wirebonds are the most critical step of the process of the BVA PoP. Forming the wirebonds with the tips having good positional accuracy (X and Y) and uniform height (Z) is important in enabling very fine pitch and high yield package assembly. Figure 6 shows bottom package substrate with the flip-chip attached logic chip and BVA around the periphery.

Once the wirebond connections are made, the molding is applied to the logic package, while exposing the BVA tips with a consistent desired height. A film-assisted mold technique was used here to expose the tips. The process uses mold cavities only slightly deeper than the formed copper wires. When the mold is clamped to the substrate, the tips of the copper wires are pushed into the mold film. The mold cavity is filled with the molding compound. After mold cure and the film removed, the package reveals the wire with exposed tips about 0.12mm  ±10µm.

To achieve very good solder stacking results, the wire tips are cleaned after molding and various techniques such as wet blast and chemical etch were used. The best conditions were obtained with wet etch (Figure 7).



Finally, the stacking of the memory package on top of the logic package is performed (Figure 8). This process is very similar to conventional PoP assembly where solder paste is printed on the main board; the logic package is placed on the board; the memory package is dipped in solder flux and placed on top of logic package, and the stack is reflowed along with other components on the board. Reliable joints were obtained across all interconnects over the whole package (Figure 9).

Extensive reliability tests were performed on the PoP stack, and the results are shown in Table 3. The tests illustrate the high reliability of the BVA process. It is worth noting that the drop test was extended up to 128 drops without observing any failures.



[Ed.: To enlarge the figure, right-click on it, then click View Image, then left-click on the figure.]

The copper-tin diffusion between the copper wire and the solder ball was studied by an accelerated testing of the amount of intermetallic formation under high-temperature storage test (3x solder reflow cycles followed by 230 hr. at 175⁰C). The copper wires were coated with palladium to stop the intermetallic formation. Figure 10 shows that wet etch method has not damaged the wire tip palladium coating, which has served as an effective barrier against intermetallic growth. In the contrary, the wet blast method has damaged the palladium coating, leading to extensive intermetallic growth.

Summary

The XFD and the BVA technologies discussed here provide enough headroom in interconnectivity and provide low power bandwidth to bridge today’s die or package stacking technologies for many years to come. These two technologies are available today and can be easily manufactured using standard available infrastructure.

Belgacem Haba has a Ph.D. from Stanford University and is vice president and senior fellow at Invensas (invensas.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Last Updated on Monday, 04 March 2013 16:44
 

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