Design and Modeling of High-Speed, High-Density 3-D CSPs and Memory Modules Print E-mail
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Written by By Frank Y. Yuan, Ph.D., and Richard Crisp   
Monday, 31 March 2008 19:00

Challenges and technologies of high-speed memory systems.

DDR2 pushed memory clock frequencies to 400 MHz and data rates to 800 Mbps. DDR3 further pushes clock frequencies to 800 MHz, while DDR4 is up to 1.6 GHz. New packaging technologies such as die stacking and package-on-package (PoP) are being developed as well. Here, we demonstrate the design, electrical modeling and testing of a high-speed, high-density DDR2 DIMM module using stacked packages. We designed and modeled a single metal layer DDR2 package, known as Micro Pin Interconnect Layer (µPILR). Next, we evaluated the electrical performance (including power and ground distribution networks) of a four high package-on-package (PoP) stack of µPILR CSPs using detailed 3-D modeling and extraction. Then, this PoP electrical model was used to design an 8 GB DDR2 DIMM. We combined the PoP model with a DIMM connector model and PCB interconnects models to form the complete channel link model. Pre-layout timing and signal simulation results were used to guide the DIMM design. The completed DIMM was thoroughly simulated and analyzed to ensure the timing and signal integrity requirements before release to manufacturing.

To further explore opportunities for applying the novel packaging to meet projected future needs for DDR3 and DDR4 data rates, we extended our modeling research using the above methodology to look at even higher clock frequencies and data rates. Results show that wire-bonded µPILR PoP stacks are capable of handling data rates of 4 Gbps and higher. A test platform was built to study and measure the memory interconnects topologies at higher frequencies and also validate the software simulation results. We then looked at limitations associated with multiple slot, multiple DIMM configurations.

Limiting the Slot Number

There are many technical challenges for building high-speed, high-density memory modules. Signal and power integrity are crucial factors that must be modeled and analyzed carefully in the design process, as they influence memory operating speed and electrical performance. High-speed I/O buffers must use low voltages, and have low switching noises, low input/output capacitances and good on-die termination. System topology and configuration affect the overall bus speed due to stub and loading effects. A single slot configuration can operate at a very high speed, yet is limited in capacity, while a four-slot configuration would significantly reduce operating speed but increase memory capacity. A solution is to limit the slot number (to two or fewer) while increasing the module capacity to achieve higher speed and density at the system level. This requires a solution that can stack two, four and even eight dice in the same form factor with better high-speed performance at comparable costs and manufacturing infrastructure.

We found the novel PoP stacking for DRAM significantly increases the memory density within a single package footprint, thus increasing the total DIMM capacity, while maintaining good signal integrity for higher frequency operation. This is an electrically superior topology compared to multiple DIMM slots with the same total system memory. In a stacked DRAM configuration, multiple dice can be active simultaneously, drawing larger current and potentially generating larger power and ground noises. To overcome this possible limitation, the package’s fine pin pitch permits higher I/O pin density and the addition of pins for power and ground nets to reduce power and ground inductance. A µPILR PoP solution permits single die/layer testability, resulting in high package and assembly yields.

3-D CSP Design

A wirebond µPILR package was designed for a 1Gb 800MHz DDR2 die. This package used a single metal substrate with FR-4 material, a pin pitch of 0.5 mm and a copper pin height of 125 µm (Figure 1). Special attention was focused on critical nets and the power and ground nets. The differential clock and strobe nets are routed as co-planar lines with 65V impedance, and are well separated by power and ground from other signal nets. Wide trace and semi-planes are used for power and ground nets. The single substrate packages are then stacked to form a four-high stacked µPILR PoP for high-density DDR2 application (Figure 2 and Figure 3).

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To accurately and fully evaluate the electrical performance of the package at very high speed, a full 3-D electromagnetic model extraction was carried out. The complete details of the 3-D package, including various package materials and conductors, were incorporated into an Ansoft 3-D solver. Package RLC parameters were calculated for different traces, as well as power and ground nets. A multiport equivalent circuit representing the entire package was obtained. This modeling process enabled evaluation of the package design’s electrical characteristics and performance, and use of the equivalent circuit as a building block for overall total system design and simulation.

As stated, power integrity is critical in the stacked package since all four dice can be active simultaneously. The transient current and power to ground loop inductances mostly determine the power/ground switching noises, as indicated by Eq. 1.

dV = L di/dt        (Eq. 1)

To calculate the power to ground inductance, the 3-D power and ground connections in the package, including the bond wire, substrate metal and stacking pins were modeled (Figure 4). The power and ground inductances for the novel package are 1.48nH and 1.50nH, respectively, and for the standard BGA 2.89nH and 1.95nH, respectively. The novel package significantly improved the overall power integrity.

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After design, modeling and optimization, the four-stacked novel package was used in the design and build of a high-density, high-speed 8GB DDR2 DIMM module. The RDIMM was designed based on a modified JEDEC Raw Card M configuration. The DIMM board is double-sided with nine stacked novel DRAM packages on each side, and complies with standard form factor. As a result of a high routing density and tight trace length matching requirements, a buildup 14-layer FR-4 PCB was chosen. This enabled stripline routing with good controlled impedance and separation for high-speed nets. The two top and two bottom layers used laser-drilled microvias for fan-out of the 0.5 mm pitch package pin field.

Accurate modeling and comprehensive simulation for timing and signal integrity are essential for such complex, high-speed system design. A simulation platform was built using HSPICE and Ansoft Designer. Both SPICE and IBIS driver/receiver models were obtained for the DRAM die, register and memory controller. A total link channel model was constructed with DRAM I/O, the novel PILR package, DIMM board via and traces, DIMM connector, main board PCB traces and the memory controller package and I/O. Pre-layout topology explorations were done for the critical clocks, DQS, DQ and address/control nets to generate layout guidelines and routing rules, and to quantify timing requirements in terms of trace length and loading condition.

Figure 5 shows the schematics of clock distribution net in our pre-layout simulation. Figure 6 shows a typical clock signal waveform. Notice in the four-stacked design, there are quadruple clock drivers/receivers on the same net vs. a regular single package design. The increased loads slowed down the clock edge, thus changing the timing skew. Also, the multiple branches produce more signal reflections and require careful optimization of the termination resistors through simulation. Identical simulation analyses were applied to other critical nets.

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After board layout was performed according to the guidelines, a post-layout simulation was carried out to verify the design in the real physical structure. The actual link topology, including trace geometry, layer stack-up and vias, was extracted and then simulated. For example, Figure 7 shows the actual CKE net trace layout, and Figure 8 shows the corresponding signal waveform.

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Finally, the 8GB DIMM test vehicle was built and tested successfully. This proved the novel PoP’s capability for stacked DDR2 high-speed, high-density memory application.

DDR3/DDR4 Memory Systems

To explore future application of the novel PoP for DDR3 and DDR4, we extended the modeling and simulation methodology to study the package and interconnect structures at even higher speeds. Also, a hardware test platform with the same memory interconnect topology was built. PRBS signals from the signal generator were connected to the bond wire side of the DRAM package, and the eye diagram was measured at the memory controller package. The test results were then compared to simulation results to validate the simulation platform (Figure 9a and Figure 9b). Except for the somewhat more pronounced overshoot/undershoot in the simulation results, most likely caused by an underestimate of system loss factor, the measurements and simulation agree well.

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For practical DRAM packaging, a key question was whether wire bond would work in higher speed DDR2/DDR3 and even DDR4 applications, or if a more costly flip-chip package is necessary. Our DIMM design proved wire bond is sufficient for DDR2 800MHz. Using the test platform, we studied wire bond vs. flip-chip packages at much higher speeds in the DDR3/DDR4 range. Figure 10 compares measured eye diagrams for wire bond vs. flip-chip at a 3.3Gbps data rate with 4pF load capacitance, while Figure 11 compares them at 6.0 Gbps with 2pF load capacitance. The impact on signal quality due to wire bonding can be seen at around 6.0 Gbps, which is much higher than the speed range of concern. Also noteworthy is the I/O load capacitances have a much greater effect on signal deterioration.

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Future work will focus on generating and analyzing more detailed power and ground distribution system models, and simulation of SSO and interconnect using actual DDR3 and DDR4 device information.

Frank Y. Yuan, Ph.D., is a principal engineer and Richard Crisp is director of high-performance packaging and applications at Tessera Inc. (tessera.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

 

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