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Sunday, 31 August 2008 19:00
Technical Abstracts Medical Electronics

“Reliability Considerations for Implantable Medical ICs”

Authors: Mark Porter, et al; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Abstract: Traditionally, implantable applications have taken a fast-follower approach to silicon adoption, using more mature technologies to reduce risk. While commercial manufacturers, in some circumstances, may be able to trade lifetime requirements for performance, this is decidedly not the case for implantable use, for which 10- to 12-year requirements are typical. On the other hand, hardware and software redundancy solutions employed by high-reliability avionics, telecommunications, and servers are difficult to implement in a battery-powered device, where current drain restrictions are severe. This paper discusses some of the reliability challenges faced by implantable device manufacturers. (IEEE International Reliability Physics Symposium, April-May 2008)

Package Reliability


“Impact Of IC Wafer Fab and Assembly Fab Processes on Package Stress-Induced Product Reliability Issues – An Insight into the Package Stress Relief Design Rules by Simulation”

Authors: Y. Li, M.A.J. van Gils, W.D. van Driel, R.B.R. van Silfhout*, J. Bisschop, J.H.J. Janssen and G.Q. Zhang; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Abstract: In this work, the impact of the layout of the top metal of the IC and most relevant process and material parameters of IC wafer fab and assembly fab on package stress-induced damages to the ICs during temperature cycling is studied by means of thermo-mechanical simulations with experimental verifications. Besides die size, the materials for passivation, silicon thickness, molding compound properties, cohesion between the molding compound and die surface, and lead frame yield stress, all are found to significantly influence the risk of damages or failures on the IC surface. The results suggest a more complete package stress relief design rule, pointing to a systematic approach to eliminate or suppress package stress-induced damages to the IC and, consequently, a possibly more efficient use of the silicon area in IC design. (IEEE International Reliability Physics Symposium, April-May 2008)


“Electrical Characterization of Plastic Encapsulations Using an Alternative Gate Leakage Test Method”

Authors: M. van Soestbergen, et al; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Abstract: The supply current of plastic encapsulated devices in the presence of a high potential source can increase abnormally due to parasitic gate leakage. Stress during a parasitic gate leakage test is applied by a corona discharge at a thin tungsten needle placed a few centimeters above the devices under test. The gate leakage sensitivity factor obtained from this test lacks any physical basis and is, therefore, not believed to be useful. This paper shows this sensitivity factor can be replaced by a physical model for charge transport through the encapsulation material. The model is used to explain why devices encapsulated by a molding compound with a low-volume resistivity of 6x1011 Ohm-cm at high temperature (150°C) are more prone to fail the test on an increased current, compared to devices encapsulated by a compound having a high resistivity of 4x1013 Ohm-cm at the same temperature. Also discussed is an alternative test setup, where the potential difference between two parallel electrodes sandwiching the devices is used as the source of stress. Using both setups on the same product did not result in an equal outcome, which indicates both tests do not trigger the same failure mechanism to the same extent. (IEEE International Reliability Physics Symposium, April-May 2008)

Solder Reliability

“Metallurgical Analysis and Hot Storage Testing of Lead-Free Solder Interconnects: SAC verus SACC"

Authors: Daniel T. Rooney, et al; This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Abstract: It is believed rare earth element additives refine the microstructure of the solder and improve the mechanical durability and thermomechanical integrity of Pb-free solder joints. This paper presents the results of a comparative analysis of solder joints with the common SAC 305 alloy (Sn 3.0% Ag 0.5% Cu) and a SACC alloy (Sn 3.0% Ag 0.5% Cu 0.019% Ce), which contains a small concentration of a cerium additive. The influence of cerium on the microstructural refinement of the bulk solder; the metallurgy of the intermetallic compounds; and the damage evolution of the solder during thermal aging tests are investigated. This change in the fracture surface morphology suggests cerium additives improve the mechanical integrity of the bulk solder, and correlates with previous materials testing on bulk solder samples of SACC and SAC, which show SACC solder has a higher Young’s modulus (higher stiffness), higher yield stress and higher strength over a wide range of strain rates and temperature conditions. On the other hand, in the hot storage tests, the SACC samples exhibit thicker intermetallic formations at the bulk solder to component interface than in SAC samples, which suggests SACC alloy solder joints could be less mechanically robust than SAC solder joints under dynamic loading conditions such as drop testing. (Electronic Components & Technology Conference, May 2008)

Circuits Assembly provides abstracts of papers from recent industry conferences and company white papers. With the amount of information increasing, our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.

 

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