‘Bump’ing Up Coverage Print E-mail
User Rating: / 0
PoorBest 
Written by Stacy Kalisz Johnson   
Tuesday, 30 September 2008 19:00

A novel soldered probe could improve access at ICT.

Test and Inspection Test access continues to be an issue, especially for in-circuit test, which is fundamentally dependent on electrical access. One way to battle the access issue at ICT is through Bead Probe technology. This novel method is steadily becoming more mainstream, and the number of licensees increasing rapidly.

Bead Probes enable us to look at test access in a new way. A Bead Probe, which is a soldered bump (Figure 1), can be placed directly onto copper signal traces. The bumps are added using existing solder paste printing principles, reflowed using standard procedures, and then serve as the probe test point for ICT access. Beads are layout-independent (i.e., they can be added after copper layout without the need to move or modify traces) and use standard ICT methods. The bumps also merge the world of the process engineer with the test engineer – a long separate bunch of folks! This month, I explore some of the recent discoveries with using these novel bumps in a manufacturing environment. As with anything new, education, experimentation and practice will make perfect.

Image

The bump locations need to be entered into the design. To do this, users either assign a bump location as pad geometry (normally looks like a via) or assign as a surface mount component. There are board design considerations as well. Keepout areas around components and component outlines need to be validated and respected. That said, costly re-routing of signal paths during layout to accommodate traditional test pads would not be needed. It is important to confirm the CAD denotes openings in the solder mask for the bump locations. Commercially available tools exist to automate this with no modifications to copper and with the keepouts and restrictions automatically maintained.

When doing any test and inspection, there are always CAD translation considerations to plan for. The method the layout engineer used to define the bump locations, as mentioned, needs to be known, as well as the side of the board the individual locations have been assigned. As with any utilization of CAD, being able to identify the x-y locations of the bumps will be necessary.

For years process engineers have studied the impact of solder paste types on printability and flux residue. Ideally the bump print deposition would be inspected using solder paste inspection or AOI to ensure print robustness and repeatability. In fact, while implementing the bump technology, users can also help identify other process issues. The photos in Figure 2, for example, are from the same board, showing obvious solder problems causing the issues noted. Flux residue on the bumps may impact contact with the probe. Minimizing residue for bump implementation is necessary and attainable with test friendly solder pastes. Process engineers have worked hand-in-hand with bare board suppliers to keep solder mask tolerances in check. These are now considerations the test engineer needs to investigate when implementing soldered bumps as well.

Image

Fixture vendors need to be a partner in soldered bump development. Implementation has the potential to change the fixture cost. In some cases, if the bump locations are on the fixture top, costs may increase, but in turn more probing options may reduce fixture cost. Flat-faced probes are ideal. Headed or headless can be used. Headless probes permit guided probe techniques.

As with any new technology, education is critical for success. Like characterizing a new solder paste or implementing 01005 placement, process design and characterization are a must. Boning up on process engineering skills such as using test-compatible solder paste to minimize flux residue, and working with the bare board manufacturer to keep solder mask opening tolerances, will ease soldered bump implementation. Users need to work with fixture suppliers to ensure proper probe selecting and seating, which are critical. Successful implementation requires synergy among design, test, fixture, bare board and manufacturing. This synergy will provide an opportunity to opening access and in many cases provide better coverage.

Stacy Kalisz Johnson is Americas marketing development manager at Agilent (agilent.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

 

Columns

Eastern-US: China’s New Competitor?

Parity emerges among EMS Factories from Asia, Mexico and the US.

For the first time in years we see parity in the Eastern US among EMS factories from Asia, Mexico and the US. This EMS market condition will permit American OEMs (the EMS industry refers to OEMs as customers) to have more EMS pathways to choose from. Now more than ever, such EMS assignments will require deeper investigation relating to the OEMs’ evaluation of manufacturing strategies.

Read more...
 
The Human Touch

For those who count on the electronics industry for big feats, it’s been a remarkable couple of years.

Read more...
 

Features

Advances in Concentration Monitoring and Closed-Loop Control

Contaminated bath water skews refractive index results. New technology can accurately measure aqueous cleaning agent concentration.

Read more...
 
Circuits Disassembly: Materials Characterization and Failure Analysis

A systematic approach to nonconventional methods of encapsulant removal.

Read more...
 

Search

Search

Login

CB Login

Language

Language

English French German Italian Portuguese Russian Spanish
 

Products

Yincae Rolls Out ACP120 Solderable Coating
ACP 120 series anti-oxidation solderable coatings replace nanofilm gold. Are for anti-corrosion and anti-rusting on solderable surfaces on which solder paste, solder preform or a solder ball can be...