| Overcoming Limited Access at ICT |
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| Written by Jun Balangue | |||
| Wednesday, 31 December 2008 19:00 | |||
A case study on test access on high complexity components on motherboards.Higher pin counts on CPU sockets and BGA devices, along with high-speed differential signals, pose challenges to existing in-circuit test of motherboard assemblies. They include:New generation CPU sockets consist of about 55% signal pins. Most of these signal pins are high-speed differential signals no longer accessible for ICT probing (Figure 1).  Smaller motherboards, causing constraints in PCB size and loss of ICT access. Too many ICT probes under the BGA devices or CPU socket can result in solder ball cracking (Figure 2).  Lowering test cost without sacrificing coverage. Agilent’s novel VTEP (Vectorless Test Extended Performance) technology and boundary scan are the main building blocks for another novel technology that extends coverage. VTEP, an unpowered vectorless test method, uses a stimulus signal driven by the in-circuit probe using a sensor plate to measure the capacitance between device pins or BGA balls and the board pads (Figure 3).1 VTEP requires physical test access (i.e., test probes) to deliver this stimulus signal. With the novel Cover-Extend technology, however, the stimulus signal is delivered via a boundary scan device.  Boundary scan is a global standardized test methodology (IEEE 1149.x standard). It provides limited-access capability – i.e., the ability to control I/O functions of individual pins through the use of only four pins on the test access port (Figure 4).  Cover-Extend works as follows:
This method minimizes the number of probes required to test the assembly (Figure 5 and Table 1) with the same test coverage using a combination of VTEP and boundary scan.   Motherboard case study. The latest generation of motherboards consists mainly of CPU sockets, I/O, BGA devices and power circuitry, with about 50% of the total targeted testable pins and solder balls CPU sockets and connectors. Traditionally, CPU sockets and connectors are tested at ICT using vectorless testing. However, these test strategies are eroding, as designers are not able to place test points in every signal pin and solder ball on the motherboard, forcing test engineers to look for an alternative strategy. Figure 6 shows results from a study using the novel method on an Agilent Medalist i3070 ICT. The data show the difference between good signal pins and open pins.  Notebook motherboard case study. New generation notebook motherboards are seeing dramatic changes in design, driven by cost pressure, size reduction, as well as demands for longer battery life and increased performance. Notebook motherboard PCBs will continue to shrink in size, even as they need to be able to accommodate the new generation of CPU and BGA devices and meet the various demands mentioned above. Figure 7 shows the number of pins tested using the novel method, with pin coverage of 45% (370 of the total 818 signal pins) on the connectors. In reality, Cover-Extend pin-count coverage includes not only connector pins, but also pins of upstream boundary scan devices used to drive the signal for the novel method. Table 2 also shows the number of ICT probes removed compared to VTEP only, which requires ICT probes to every target pin to be tested.   Server motherboard case study. Server motherboards present the most potential for the novel technology because of the tremendous number of connector pins. The current server motherboard design still lacks the full capability to maximize the novel technology, as most of the BGA devices are not enabled for boundary scan. If the connectors on the server motherboard are to be 100% tested using the novel method, the coverage will also extend to upstream boundary scan devices (Figure 8).  Figure 9 shows how the novel technology reduces the number of ICT probes needed to test all the board components. ICT system cost will be reduced, as the number of hybrid cards required to test a server motherboard with more than 4,000 nodes also will be reduced (Figure 10).   The method also will reduce potential solder ball crack occurrences under the BGA and CPU socket, as the number of ICT test probes needed will be reduced almost by half, minimizing PCB strain. Reference
Jun Balangue is technical marketing engineer at Agilent Technologies (agilent.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
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| Last Updated on Friday, 02 January 2009 06:16 |
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