Determining Current Carrying Capacity Print E-mail
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Written by Jack Olson   
Tuesday, 01 December 2009 00:00

Understanding the new standard for predicting temperature rise.

Determining appropriate trace sizes for current requirements is an important aspect of board development. Since copper is not a perfect conductor, it presents a certain amount of impedance to current flowing through it, and some of the energy is lost in the form of heat. For many applications, it is necessary to predict the temperature rise caused by this loss, which traditionally has been accomplished using a chart created over 50 years ago by the National Bureau of Standards (IPC-2221, Figure 6-4), or by using one of several calculators based on it. The chart shows the relationship between current, conductor temperature rise and conductor cross-sectional area. If any two of these are known, the third can be approximated.

About 10 years ago, Mike Jouppi, then of Lockheed Martin, began performing experiments to examine the accuracy of this chart, because the predicted temperature obtained from it did not correspond to the data he was measuring on actual product. From these new data, he developed several new charts, which have been verified by a parallel study performed by the Naval Surface Warfare Center, Crane Division.

The results of both studies were compiled into IPC-2152, “Standard for Determining Current Carrying Capacity in Printed Board Design.”1 From the data in this new document, a method can be established to predict the temperature rise of a board trace more accurately, taking into account the effect of several variables such as board thickness and material, internal vs. external traces, still air environments vs. vacuum, and proximity to heat-sinking planes.

Estimations using these new data can be far more reliable than previously possible, without the use of more sophisticated thermal analysis tools.
IPC-2152 contains over 90 new charts in addition to the now infamous historical chart, but before exploring the new data, a few aspects of the historical chart should be understood. When the chart was created in the 1950s, there were no multilayer boards, and all the data were taken from surface traces. No one is sure where the internal chart came from, but it is thought that when multilayer board constructions became practical, the external values were merely doubled to get values for internal traces. This has since proven inaccurate. The thermal conductivity of FR-4 is better than air, so in a still-air environment, internal traces run cooler than external ones. The internal values are so conservative, however, that designers haven’t experienced problems using them, except for the large amount of board real estate needed to implement the recommendations.

An interesting result of the new study is that, although the values for internal traces were not scientific, by coincidence they very closely approximate the behavior of traces in free air.  The new data also show the external trace chart only was safe for boards greater than 3 x 3˝ and with planes, so it was decided to remove the historical chart for external traces from IPC-2152. Recommendations for external traces can be easily obtained with the new charts and adjusted for the proximity to heat-sinking planes.  

Because the internal chart values approximate the temperature rise of a trace in free air (which can be considered a worst-case scenario), it was decided to use it for the most conservative chart (Figure 1). Values obtained from this chart are very safe and will work in any circumstance except vacuum, regardless of other variables.



For example, let’s say a trace in a very thin flexible dielectric must carry 4 A continuously, and you want to limit the temperature rise to 10°C over ambient. To use the conservative chart, follow the 4.0 A current line across until it intercepts the 10°C temperature curve. Follow that intersection down to find the recommended cross sectional area of 0.300˝2. This cross-sectional area can be refined further by modifying it with known design constraints. These adjustments are described in Modifying the Chart Value.

After the recommended cross-sectional area is determined, it can then be converted to appropriate trace widths (based on the copper thickness used in the design) by using a chart presented later in this article.

Figure 1 provides very safe estimates for most applications. For a more precise estimate based on specific design constraints, new charts have been developed. Since board development often depends on common laminate materials with common copper weights, separate sets of charts are provided based on 0.070˝ polyimide material with 3, 2, 1 and 0.5 oz copper in still air. For each of these, there is a primary logarithmic chart (Figure 2). Figure 2 is the baseline chart for 3 oz. copper, which is the universal chart used in IPC-2152, Figure 5-2, and recommended for both internal and external traces.

 
Since logarithmic charts are difficult to read, three additional charts that show temperature curves at successively finer resolution follow each of these primary charts. This has been duplicated by another complete set of charts for vacuum environments, and all these are duplicated again to provide versions for inch and metric units. (There are also charts in the appendix for internal vs. external traces.)

(For the purposes of this tutorial, we will look up a starting value from the universal chart and then modify it for our particular design constraints. If you have the extra charts in IPC-2152, you can select a chart more specific to your application, and skip the corresponding modification outlined below.)

Obtaining the Appropriate Chart Value

The first step in estimating appropriate trace widths is determining the acceptable temperature rise. This is an important point, because most board designers are familiar with “ambient temperature,” a simple term that describes the environment in which the electronics assembly operates. For our application, “ambient temperature” can be misleading, because the temperature rise of the trace is going to be higher than all the contributing factors combined. This is not just the ambient temperature; it is the ambient temperature plus all the other heat sources of nearby components and traces.

For this reason, the new standard prefers the term “local board temperature” to “ambient temperature.” The local board temperature can be significantly higher than the surrounding environment, and the temperature rise of a single trace is added on top of that. For example, the product may be required to operate in an ambient temperature of 125°C, and the area of the trace evaluated may have power devices and other high current traces in close proximity. The local temperature already may be approaching the maximum continuous operating temperature of the board material itself, and a lower temperature rise may need to be defined for the single trace. (Parallel traces are a critical factor that should not be ignored. The added temperature from surrounding traces can have a significant effect on the local board temperature, and should be considered in every evaluation. IPC-2152, Appendix A.3.3, discusses this in detail.)

In general, traces operating at high temperature waste power and add thermal stress that may lead to early failure, so a low temperature rise should be a design goal whenever possible.

Once you have settled on an acceptable temperature rise for the trace being evaluated, it is a simple matter to find the cross-sectional area required for the current requirement, using either the conservative chart or the new universal one. (Use the new one only if your board is greater than 3x3˝!)

Modifying the Chart Value

If the conservative chart (Figure 1) was used to obtain the starting chart value (CV), it can be used as is, without additional analysis. If the universal chart (Figure 2) was used to obtain the CV, keep in mind that it is based on a board that was constructed with 3 oz. copper on polyimide 0.070˝ thick. To get a more accurate estimate, several modifications may be performed to the CV. The easiest way is to start with a modifier of 1.00, then add or subtract based on the following paragraphs to get the final modifier, then multiply the modifier and the CV to get the modified cross-sectional requirement.

Start with a modifier of 1.00, and go through the following steps:

1. Copper thickness modifier. If the universal chart was used to obtain the CV, and something other than 3 oz. copper is used, take advantage of the fact that for the same cross-sectional area, thinner copper has more surface area and is therefore better at dissipating heat. Thicker copper will have thinner trace width for the same cross-sectional area, less surface area, and will operate at a higher temperature (Figure 3).

2. Plane modifier. Because the proximity to heat-sinking planes has such a drastic impact on the temperature, the presence of planes will cause the most significant adjustment to the CV. For boards with a 1 oz. plane that is at least a 3 x 3˝ area (directly under the trace being evaluated!), use Figure 4 to determine the modifier:

For 2 oz. planes, subtract another 0.04 from the modifier.

For planes greater than 5 x 5˝, subtract another 0.04 from the modifier.     



3. Board material modifier. The polyimide material used in the study has a thermal conductivity of 0.0138˝, and FR-4 is slightly worse at 0.0124˝, which makes a difference of about 2% in the CV. Materials with different thermal properties may influence the recommendation. For FR-4 boards, add 0.02 to the modifier (Figure 5).



4. Board thickness modifier. The new charts were constructed using data from 0.070˝-thick boards. Thinner boards will be hotter, and thicker boards will be cooler (IPC-2152 A.4.2) (Figure 6).  



5. Altitude modifier. This one may be refined in the future, but knowing that air is thinner at higher altitude, and traces run 35 to 55% hotter in a vacuum, either the conservative chart should be used or the CV should be increased for high-altitude designs.

6. Derating modifier. Keep in mind the charts have no derating applied, but many variables may affect the CV prediction and should be considered for marginal designs. For example, the planes modifier is based on the assumption that the trace sits over a solid plane, but in actual practice may be located near a board edge or over a plane that has clearances in it for through-holes or plane splits, which will be less effective in dissipating heat. Process variations that affect the trace geometry may also influence the results (in the form of voids, nicks, overetching, final plated conductor thickness, etc.). These variations all have acceptable tolerances in the finished product, but may affect the estimated temperature rise. It is advised that some amount of standard derating be applied to the CV – 5%? 6%? – but a full examination of this modifier is beyond the scope of this article.

7. Environmental modifier. The new data describe traces in still air (which assumes some amount of natural convection), so these recommendations should be valid even for applications inside a sealed enclosure. But for many other applications, airflow will be present, and this additional heat transfer may allow a reduction in cross-sectional area. This is a complicated subject, and recommendations related to airflow are beyond the scope of this article.
Some thermal analysis may be needed if the designer needs to use thinner traces than what the available data suggest.

Obtaining the Final Trace Width

At this point you have selected a value from one of the charts and modified it for your specific design parameters. Multiply the starting CV with the final modifier to get the final recommended cross-sectional area for the application.

The final step is converting the resulting cross-sectional area to the final trace width, based on the thickness of copper used in the board construction. This step should not be confused with the modification based on copper thickness to account for varying surface area. Figure 7 is a direct correlation between cross-sectional area and (copper thickness x trace width):

For example, assume the design of a four-layer FR-4 board that will be 3 x 5˝ by 0.063˝ thick, and the two internal layers are power and ground planes that are 0.020˝ away from the surface layers. We need a trace that can accommodate 4 A continuously, and we want to limit the temperature rise to 10°C above the local board temperature.



We could use the conservative chart to get a 0.300˝2 cross-sectional area, and use the final conversion chart for 1 oz. copper to get:

Trace width = 0.220˝.
That’s the easy answer, and if the board design allows, it can be used as is. Because we have good information about our design, and the board is larger than 3 x 3˝, the universal chart can be used instead. Following the 4 A line across to the 10°C temperature curve, we see that it intersects with the line for a starting value of 0.200˝ cross-sectional area.

CV = 200, starting modifier = 1.00

Next, we can modify based on 1 oz. copper:
Modifier = 1.00 – 0.14 = 0.86

Because we have a 1 oz. plane 0.020˝ away, using the Planes Chart, we get:
Modifier = 0.86 – 0.53 = 0.33

Our board thickness of 0.062˝ is less than 0.070˝, thus using the Thickness Chart:
Modifier = .033 + 0.10 = 0.43

We are using FR-4 instead of polyimide, so using Material Chart:
Modifier = 0.43 + 0.02 = 0.45

And as a judgment call, we add 3% for derating:
Modifier = 0.45 + 0.03 = 0.48.

Now we modify our starting 0.200˝2 chart value:
200 x 0.48 = 96

Using the final chart to convert 0.096˝2 to a 1 oz. trace width, we get:
0.007˝ trace width.

The historical chart would have recommended a 0.095˝ trace width for a 4 A, 1 oz. external trace, which illustrates how the new data can be used to push the envelope. In many cases, the design can have less board space, using appropriate parameters to derive the estimate.  

References
1. IPC-2152, “Standard for Determining Current Carrying Capability in Printed Board Design,” August 2009.

Acknowledgments

Thanks to Borko Bozickovic for help in analyzing data and developing charts, and to Mike Jouppi for making it all happen.

Jack Olson, CID+, is a circuit board designer at Caterpillar Inc. (caterpillar.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Last Updated on Monday, 14 December 2009 17:29
 

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