Lowering Next-Gen Silicon Product Cost Print E-mail
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Written by E. Jan Vardaman   
Sunday, 01 November 2009 00:00
  

The impacts of design, packaging, assembly and test on TSV adoption.

Over the past few years, companies have seen the price of silicon fabrication fall and the cost of packaging, assembly and test rise. Years ago, packaging only accounted for 10% of the price; today it may be as much as 30 to 40%. The greater price share taken by packaging and assembly is making many industry executives nervous about the impact on margin.

The industry’s experience with the introduction of low-k dielectrics helped corporate management understand the value of the backend process, when a host of problems were encountered during assembly, resulting in heaps of scrap. These problems have been solved, and the packaging engineer’s status elevated. Today companies talk about bringing together all parties in the process to ship the next device, and the need for communication among all parties is clear. There are many discussions about co-design and co-simulation, the most recent during a panel held Oct. 1 at SEMI’s Known Good Die Workshop in Santa Clara, CA. The need for co-design will be even more pronounced as the industry adopts 3-D through silicon via (TSV) technology in production for a variety of products.

At the IEEE 3-D IC conference held in San Francisco during the last week of September, it became clear the pace to introduce 3-D TSV technology has ramped in the past six months. A tremendous number of developments have taken place in multiple research institutes, companies and universities around the globe. Close to 20 members of Japan’s ASET program (the largest single contingent) presented developments related to co-simulation between the circuit simulation and electromagnetic simulation, interposer technology, inspection, thin wafer singulation, as well as chip test technology for 300 mm wafers focused on contact and non-contact probe cards. Researchers from IMEC discussed the institute’s inclusion of test and some of the many process developments in processing technology. Taiwan’s ITRI, Singapore’s IME, Korea’s KAIST, France’s CEA-Leti, Germany’s Fraunhofer Institute, Lincoln Labs and other US research organizations participated by sharing some of their progress. Scores of participants from companies such as IBM, Intel and many fabless companies conversed with equipment and material suppliers to provide clear evidence of progress in the technology. It is no longer a matter of if but when the adoption in each application area will take place.

As 3-D silicon progresses from stacked die and PoP to TSV, an integrated chip-package-board design methodology is becoming essential for optimizing the system in a way that cannot be achieved with serial design. Co-design and co-simulation allow decisions to be made early in the process, while the cost of change is still low, and ultimately this approach can optimize performance while reducing design iterations, design time and product development cost.

TechSearch International’s surveys and recent panel discussion show that designers and EDA vendors agree the barriers to co-design are many. However, conversations with both groups reveal differences on what the primary constraints are. While package designers see the problem as the lack of appropriate tools, EDA suppliers suggest designers are reluctant to make the cultural changes necessary to take full advantage of co-design. On the user side, chip and package suppliers say there are excellent point solutions for design of the chip, package and board, but they are not integrated. The lack of a common format among different EDA suppliers is a significant barrier. Even if an EDA vendor does offer a co-design tool or data exchange format, neither can be used if the IDM uses one vendor’s tool for package design and another vendor for IC design, which is typically the case. Additionally, the tools used by the IDM’s customers for system and/or board design are also different.1

In many cases, such as with the use of TSV technology, an entirely new architecture has been created and the EDA tools to design in this space do not exist. Designers need to be able to think and design in a third dimension with vias connecting the layers created by the combination of multiple die and interposers. Via placement becomes critical and new wiring designs must be developed. New modeling and simulation tools also will be required. The co-design panel at the KGD workshop focused on critical issues the industry faces, even for just today’s package design, much less the 3-D TSV designs. There are different tools for silicon design, package design, and board design, and these tools need to talk to each other – a challenging task. Today, things don’t really work together. Everything needs to be designed with the system architecture in mind. Managing the system netlist is important, and all the data need better managing. At times, simulation moves at glacier’s pace, but the design can’t wait three weeks for this input. Electrical tools and thermal design must all be linked. A system floor-planning tool is needed, and companies such as R3Logic are planning to offer this on a commercial basis, but it takes time. Potential EDA users are expected to help drive faster development of tools.

The co-design panel at the KGD workshop focused on critical issues the industry faces, even for just today’s package design, much less the 3-D TSV designs. There are different tools for silicon design, package design, and board design, and these tools need to talk to each other – a challenging task. Today, things don’t really work together. Everything needs to be designed with the system architecture in mind. Managing the system netlist is important, and all the data need better managing. At times, sim-ulation moves at glacier’s pace, but the design can’t wait three weeks for this input. Electrical tools and thermal design must all be linked. A system floor-planning tool is needed, and compa-nies such as R3Logic are planning to offer this on a commercial basis, but it takes time. Potential EDA users are expected to help drive faster development of tools.

3-D IC test also is undergoing ample discussion. While some argue that built-in self test and redundancy will solve any issues, others talk about the need for probe cards to handle thin wafers with micro bumps. What is clear is that the design phase is critical and DfM and DfT are going to become more critical as TSV technology is adopted.

While not everyone can agree on the order of the adoption of TSV technology by application, no one doubts that there will be a time and place. Driving down the cost will be key to adoption in most cases, and co-design will need to be part of the answer. New EDA tools, best manufacturing practices and DfT methodology are critical to TSV adoption. 

 

References
1.    L. Matthew, “Co-Design and Co-Simulation,” Advanced Packaging Update, vol. 4, April 2009.

E. Jan Vardaman is president of TechSearch International, (techsearchinc.com); This e-mail address is being protected from spambots. You need JavaScript enabled to view it . Her column appears bimonthly.

Last Updated on Wednesday, 18 November 2009 18:32
 

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