ATLANTA, GA – Georgia Tech researchers have developed a new technique for cooling high-performance integrated circuits, using microchannels integrated onto the backs of circuits to carry cooling water. The technology could allow denser packaging of chips while providing better temperature control and improved reliability.

The technique includes polymer pipes that will allow electronic and cooling interconnections to be made simultaneously using automated manufacturing processes, without damage to ICs.

“This scheme offers a simple and compact solution to transfer cooling liquid directly into a gigascale integrated (GSI) chip, and is fully compatible with conventional flip-chip packaging,” said Bing Dang, a Graduate research assistant in Georgia Tech’s School of Electrical and Computer Engineering.  “By integrating the cooling microchannels directly into the chip, we can eliminate a lot of the thermal interface issues that are of great concern.”

The approach allows a simple monolithic fabrication of cooling channels directly onto ICs using a CMOS-compatible technique at temperatures of less than 260°C.

In addition to the cooling channels, the researchers have built through-chip holes and polymer pipes that allow the on-chip cooling system to be connected to embedded fluidic channels built into a printed wiring board.  The channels can be connected at the same time the IC is connected electronically – using flip-chip bonding – and can withstand pressure of more than 35 pounds per square inch.

The system should be able to cool 100 watts per square centimeter. 

Dang expects the technology to be used first in high-performance specialty processors that can justify the cost of the cooling system. So far, the researchers have demonstrated continuous liquid flow on a chip for several hours without failure, but additional testing is still needed to confirm long-term reliability, he added. 

By eliminating the large heat sinks and heat spreaders, along with high-aspect ratio fins, the technology could allow denser packaging of integrated circuits, making 3-D packaging feasible.

The technique was presented in June at the IEEE International Interconnect Conference, and a paper will be published next month in the proceedings of ASME InterPACK.  The research was sponsored by the Microelectronics Advanced Research Corp. and the Defense Advanced Research Projects Agency (DARPA).