ARLINGTON, VA – Jedec today announced initial publication of its widely-anticipated Synchronous DDR4 (Double Data Rate 4) standard.

Jedec DDR4 (JESD79-4) has been defined to provide higher performance, with improved reliability and reduced power, thereby representing a significant achievement relative to previous DRAM memory technologies.  The new DDR4 standard is available for free download from the Jedec website.

DDR4 offers a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. In addition, the new technology has been defined with a goal of simplifying migration and enabling adoption of an industry-wide standard.

To facilitate comprehension and early adoption of the DDR4 standard, Jedec is hosting a two-day DDR4 Technical Workshop in Santa Clara, CA, on Oct. 30-31. For online registration and agenda information click here.

The per-pin data rate for DDR4 is specified as 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second.  With DDR3 exceeding its original targeted performance of 1.6 GT/s, it is likely that higher performance speed grades will be added in a future DDR4 update.  Other DDR4 attributes tightly intertwined with the planned speed grades, enabling device functionality as well as application adoption, include: a pseudo open drain interface on the DQ bus, a geardown mode for 2,667 MT/s per DQ and beyond, bank group architecture, internally generated VrefDQ and improved training modes.

The DDR4 architecture is an 8n prefetch with two or four selectable bank groups. This design will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each unique bank group. This concept will also improve overall memory efficiency and bandwidth, especially when small memory granularities are used.

In addition, DDR4 has been designed in such a way that stacked memory devices may prove to be a key factor during the lifetime of the technology, with stacks of up to 8 memory devices presenting only a single signal load.

Joe Macri, chairman of Jedec's JC-42.3 Subcommittee for DRAM Memories, said, “The new standard will enable next generation systems to achieve greater performance, significantly increased packaging density and improved reliability -- with lower power consumption.”

PCB West: The Silicon Valley's leading printed circuit design and manufacturing conference: Sept. 25-27, 2012 www.pcbwest.com