Stacked dies enable highly integrated systems in a single package. Modern microelectronics demand more functionality at chip level, smaller models, shorter time-to-market, greater reliability of design and lower cost. SOCs (system on chip) have made progress, but will soon come up against economic limits - particularly with embedded technologies for improved performance (such as when at least two different process technologies are to be integrated on the chip). This technology mix could be implemented through different chips in the most suitable technology for the respective functions, if not for the challenges connecting multi-pin chips at board or substrate level leads and complicated routing and interference. A possible solution: stacked dies made of ultra-thin silicon.

The thin, flexible silicon chips used are very demanding, highly fragile and also often warped. Suitable equipment for processing these thin dies must take account of these features.

The 2200 apm+ multi-chip die bonder features high-precision linear motors with dynamic servo-control and automatic compensation for temperature drift. High-res camera systems allow positioning precision at the xy level of ± 7 µm at 3 s and a maximum tilt of ± 0.15 ° at 3 s. Z-axis can be individually controlled for bonding functions and adhesive application. For assembly on warped substrates, an ultra-light tool's low bond force works in the 0 - 6 g ± 50 mg range.

The wafer transport system processes up to 25 different wafers with five ejection tools. Features material-protecting synchronous sequence of motions to pick the chip up from the carrier material with the help of a vacuum. Can handle small chips with edge length starting at 170 µm and, for flip-chip assembly, 500-µm chips. Automatic tool changer holds up to six different tools, including a bond head that can be heated to 350°C.

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