At last, hard data for making (and simplifying) hole-fill decisions.

This month’s cover story features a report on a wave soldering DoE produced by the late Makram Boulos of Honeywell Aerospace and a team of Celestica engineers led by Craig Hamilton. I was fortunate to be in the technical session at SMTA International when Craig presented this work last fall, and I couldn’t wait to print the paper and read it from beginning to end. A number of very good Pb-free lessons can be learned from it. Here are my top three takeaways:

It all starts with a solid DoE setup. There are two specific characteristics about this experiment I really like. First, it sets up head-to-head comparisons on factors that easily can be isolated for analysis. Sometimes our statistical software tempts us into using experimental designs that afford us more input variables with fewer runs than traditional DoEs, but if we take the bait, our overstuffed test plan can lose focus and limit our ability for point-to point comparison. This study keeps it simple and does not lose sight of its goal. The second feature that impresses me is the experiment’s outputs; they are discrete data that reflect real-world production metrics. We commonly express our outputs in experiments like these as means and standard deviations of percentages of hole fill. That’s an effective way to characterize the process, but it comes up weak on DfM guidance. To wit, 56% versus 42% average vertical fill does not provide nearly as compelling an argument for redesign as two defects versus 20. In this DoE, results are expressed in terms of defects per million opportunities (DPMO). It applies typical inspection criteria (IPC-A-610-D) to determine what is and is not a defect, and reports failure rates in terms we all can appreciate.

It shows us the money. DfM activity is much more than a rulebook for designers or a checklist for manufacturers. It’s a series of negotiations that optimize a product’s profitability by balancing design performance and manufacturing costs. Sometimes those negotiations are more challenging than others; it can be extraordinarily difficult to convince a designer to change a layout without data to substantiate the request. When solid data are available, however, the process gets a lot easier. And when those data can be tied directly to cost? Bingo – money talks! This report provides the information necessary to quantify the impact of ground tie designs, component spacing and hole-fill criteria. Simply take the defect rate and multiply it by the number of opportunities in the design and the average cost of a defect, and the decision becomes nearly emotionless; is it worth the time and money to modify the circuit up front, or is it better to pay the price for it down the road in manufacturing? (If only all DfM decisions could have such solid numbers behind them.)

It clearly illustrates the challenge of hole fill with Pb-free solders. Take a good look at the comparisons between SnPb and SAC 305 with respect to hole fill, keeping in mind SAC 305 is historically one of the top-performing Pb-free alloys when it comes to filling PTHs. Then look at the impact of specifying Class 3 versus Class 2 inspection criteria. I plucked some numbers from the paper and put them into a simple table (Table 1) to make the comparisons easy. When presented in this format, the impact of Pb-free solders and workmanship standard classification speaks for itself: Given an identical PWB design, it is easier to meet Class 3 standards with SnPb than to meet Class 2 standards with SAC 305.


I will be referencing this paper for a long time to come, and hope other readers find the same high degree of utility. It demonstrates the rewards of devising good DoEs, provides real numbers on which informed DfM decisions can be based, and makes hole-fill performance differences between SnPb and Pb-free solders absolutely impossible to ignore. This difference is of particular interest to me. As we continue to migrate to Pb-free solders, better understanding is needed of the implications of hole-fill stipulations and the reliability risk that mass rework presents to PTH barrels. (More on that next time.) In the meantime, I offer my congratulations and gratitude to the team that provided this incredibly useful information.

Chrys Shea has 20 years’ experience in electronics manufacturing and is founder of Shea Engineering; chrys@sheaengineering.com.