Larger pads and better PCB layout will reduce strain.

Pad cratering is a failure mode that consists of the fracture of the resin layer under connecting pads.¹ It is the result of excessive mechanical stresses, and is typically generated by handling. Larger form-factor boards are more prone to single overstress failures, whereas handheld and portable devices will be prone to failure after many cycles of loading.² Cracks in the laminate initiate at the corner of the pad and propagate through the underlying resin layer, leaving the pad unsupported (Figure 1). The crack path may include a connecting trace or via, which would eventually lead to electrical failure or a nonfunctional product.

Factors that contribute to pad cratering include materials, processes, design and use conditions. RoHS has exacerbated the problem, with more brittle laminate and stiffer Pb-free solders. Stiffer materials deform less under a given load, while brittle materials require less energy to fail. Different resin systems used in PCB construction also can behave very differently, even when the data sheets suggest they are similar. Unfilled resin systems typically will fail by fracturing deep through the resin, exposing glass weave when the pad is removed. Filled resin systems commonly fail very shallow within the resin layer. Data show filled systems tend to be weaker than unfilled; yet the filler provides an impedance to crack propagation, so the filled systems may perform better under repeated loading.³

On the process side, higher Pb-free reflow temperatures may induce excess component warpage and thus more stress in the interconnects. The higher temperature also degrades laminate materials more quickly, so the opportunity for cratering increases with multiple thermal excursions.
Use condition can result in cyclic mechanical loading. This occurs when the product is dropped. High strain rates caused by drop height and the bending frequency result in pad cratering that may precede electrical failures.  

Pad design is another factor that influences pad cratering. Smaller pads result in higher stress from the same load, while solder mask-defined pads may provide the additional anchoring required to prevent cratering. In a particular drop test experiment, non-solder mask-defined (NSMD) pads of 0.023˝ were compared to solder mask-defined (SMD) of 0.020˝ mask opening and hybrid “bullet” designs of 0.023˝ with an 0.008˝ x 0.023˝ SMD extension. The results showed that the test vehicles with NSMD pads failed within about 30 drops by pad cratering. Changing to SMD resulted in a change in failure to intermetallic cracking and an increase in lifetime by a factor of 2. The hybrid design has the largest solderable area, the best lifetime in drop test, and also failed by intermetallic cracking. For this test vehicle, pad cratering was prevented, and lifetime increased, by modifying the pad design. Component location is also critical; depending on the location in the board, parts may experience different stress levels. The deflection and curvature varied across board length and width, which causes different stresses at different locations.

Remedies to reduce or prevent pad cratering include optimized pad design and PCB layout to reduce strain at critical locations, as well as laminate selection and close control over the process to ensure an optimum assembly. Test methods proposed and developed for bare PWBs provide rank-order comparisons among materials, design and process.^3-6 In addition, underfill can mechanically attach components to the PCB. Full capillary and selective corner and edge bonding are methods to reduce the likelihood of cratering.

References

1. M. Mukadam, G. Long, P. Butler and V. Vasudevan, “Impact Of Cracking Beneath Solder Pads In Printed Circuit Boards on Reliability Of Ball Grid Array Packages,” SMTA International, September 2005.
2. G. Godbole, B. Roggeman, P. Borgesen and K. Srihari, “On the Nature of Pad Cratering,” ECTC, June 2009.
3. B. Roggeman et al., “Assessment of PCB Pad Cratering Resistance by Joint Level Loading,” ECTC, May 2008.
4. M. Ahmad, D. Senk and J. Burlingame, “Methodology to Characterize Pad Cratering Under BGA Pads in Printed Circuit Boards,” SMTA Pan Pacific Symposium, January 2008.
5. M. Ahmad, J. Burlingame and C. Guirguis, “Comprehensive Methodology to Characterize and Mitigate BGA Pad Cratering In Printed Circuit Boards,” SMTA Journal, vol. 22, no. 1, 2009, pp. 21-28.
6. M. Ahmad, J. Burlingame and C. Guirguis, “Validated Test Method to Characterize and Quantify Pad Cratering Under BGA Pads on Printed Circuit Boards,” Apex, March 2009.

Ursula Marquez de Tino, Ph.D., is a process and research engineer at the Advanced Process Lab at Universal Instruments Corp. (uic.com); umarquez@vsww.com. Brian Roggeman is a process research engineer at the Universal Instruments Advanced Process Lab.