Stencil design calls for three main criteria. One, the stencil should be completely flat because it needs to evenly distribute the amount of paste on all sides of the board. Two, it should be able to control solder paste spillage. If solder paste is spilled on an adjacent pad (or ball, in the case of a BGA), it could cause a short. Three, the stencil must provide optimum stability, meaning it can be repeatedly used without any issue. This could be achieved by using framed stencils versus unframed ones.
Stencil definition and design accuracy take on even greater significance when a high-count layer board is involved. In such instances, thicker boards are used for a load board application, for example, and unlike a standard six-to-12-layer commercial board, this thicker board has 20 or more layers, with more power and ground planes. This means a different thermal profile.
Stencil accuracy has a direct bearing on the thermal profile used on such a board. A thicker board, with a number of ground and power planes, requires considerably more heat for proper soldering. Also, for the same type board, a less accurate stencil design means too much or too little solder paste deposited, resulting in opens or shorts.
When a stencil is properly designed and solder paste is correctly deposited, the result is perfect printing. Put another way, this means few to no bridges or solder issues and little touchup and rework.
Special attention must be paid to devising apertures for surface mount pads on mixed signal PCB designs – in which one segment of the board is heavily analog laden, and the other digital. An analog segment requires a lot of heavy current and grounding. A thicker 0.006˝ to 0.008˝ stencil is recommended here. The thickest stencil would probably be 0.006˝ with a ratio of 1.1:1. The ratio of 1.1:1 means 10% more paste deposited compared to the pad size, thus providing a good fillet. A good fillet means enough solder is deposited, but not so much as to create a short (Figure 1).
By its nature, the analog section is a heavily ground poured area. Since heavy current is characteristic of analog circuits, those components must have extremely solid connections, either through the component side or bottom side, or internally through the ground plane. In this instance, paste deposition is called a “solder brick” (Figure 2), which describes how efficiently paste is poured on the surface mount pad. Also, a stencil for a mixed signal board must have isolation islands created to segregate current and voltage between analog and digital circuitry.
The digital side of a board with fine-pitch devices such as BGAs, µBGAs and QFNs, for instance, is another story. This calls for a ratio for paste deposits compared to the pad size of less than 1:1: for instance, a ratio of 0.9:1, which means 90% paste is being deposited. Put another way, 10% less paste is being deposited compared to the pad because the pitch is so fine. Care must be applied here because the balls of a QFN or BGA are so close that too much paste can cause a short between them.
Step Stencils
A step stencil, characterized by its different depths, is used when the application has a considerable number of analog components on one side of the board and a lot of digital on the other side. In other words, it requires different amounts of paste dispensed on different segments of the board. It provides additional paste height in certain PCB areas, and in this case, it’s called a “step-up” stencil. Conversely, sometimes, it provides lower paste height in certain PCB areas; thus, it’s called a “step-down” stencil. In other instances, where the PCB has raised areas, a “relief step” stencil is used.
As an example of a step-down stencil, consider a board with a 0.020˝ pitch QFP. A 0.007˝-thick stencil is needed for resistors, capacitors, inductors and other passives. A step-down 0.005˝-thick stencil is then used for fine-pitch technology (0.020˝) SMT devices.
A step-up stencil is used not only for analog, but also for column grid areas (CGAs or CBGAs). For example, a 0.006˝ stencil is used for capacitors and resistors. However, a step-up 0.008˝ stencil is used for CGAs or CBGAs. The extra paste height is required to support those column grid areas because they require much more paste deposition, compared to the regular SMT components on the board.
Laser-cut step-up and step-down stencils provide ideal solutions for ceramic BGA and RF shield applications. In these cases, additional solder paste deposition is required, meaning solder paste brick height is higher. As a result, it deals extremely well with non-coplanarity issues. For instance, coplanarity typically becomes an issue when an RF shield is created using HASL, rather than gold, as a surface finish on the board (Figure 3). But it’s not that much of an issue in analog or an RF board side, because the more paste deposited, the better the solder joint, especially when digital circuitry is minimal.
Thus, ceramic BGAs are one of the applications for step-up, step-down stencils. Electropolishing and then nickel plating are recommended for those stencils to achieve a good paste release for smaller aperture sizes. This stencil costs more because more processes are involved, and electropolishing or nickel plating can mean longer turnaround time.
First-article inspection is a next critical step to verify the stencil design after solder has been deposited. At this point, a determination needs to be made whether sufficient paste has been deposited for an ideal solder joint connection. Also, first-article verification step involves paste height inspection for component pre- and post-loading. Even when component placement is completed, first-article inspection should be deployed at post-placement of components. Component pre-placement inspection is performed when there’s only solder paste on the pads to verify the correct amount of paste dispensed. However, post-placement is performed when SMT components have been placed to ensure correct placement and orientation.
In some instances, the EMS provider may take a middle ground for stencil design to minimize the probability of assembly problems. Issues arise in cases like this. Let’s say the PCB layout engineer keeps the benchmark on the digital side. Based on this design, adequate paste will be deposited on pads on the digital side of the board. But it won’t be enough on the analog side, thus creating voids.
Again, as mentioned, analog requires a 0.006˝ to 0.008˝-thick stencil, while digital needs a 0.004˝ to 0.005˝ stencil. Using the wrong-sized stencil negates the concept of step stencils – to deposit the precise amounts of paste on the analog side. Also, when taking the middle ground – for example, using a 0.006˝-thick stencil for both types – the digital side may get too much paste deposition, thus creating shorts, especially when finer-pitch QFNs or µBGAs are used.
Misregistration Causes
Paste misregistration occurs for multiple reasons. The following are the most prevalent. First, the stencil aperture opening doesn’t align with the PCB. This sometimes occurs during CAM, where the proper aperture openings are not created, resulting in paste misregistration.
Also, if a PCB layout engineer is not alert or careful, they may not view the component properly to see where paste needs to be dispensed. Therefore, a layout and design engineer has to be vigilant at reading the datasheets and reviewing the component specifications.
When special components are used, it’s not always clear as to what goes on the board and what does not, or what is masked. To design proper stencils, the PCB designer has to look carefully at the physical component to ensure aperture openings are correctly defined.
Using an unframed stencil is another possible reason for misalignment. After an unframed stencil is placed on an adapter, but before it is mounted on the printer, is where damage can occur, and human interaction creates reliability issues. Also, a cleaning process must be extremely accurate during and after printing. If a stencil isn’t properly cleaned before it is archived, paste residue may be left on the apertures.
Zulki Khan is founder and president of Nexlogic Technologies Inc. (nexlogic.com); zk@nexlogic.com.