Listen: Your SPI might be trying to tell you something.

Does anybody really believe that in 2011 three-fourths of all SMT defects are generated in the print process? Of course not. But we accept this spurious, decade-old, seemingly baseless statistic on stencil printing without question because we know how important a good printing process is to a profitable SMT assembly operation.

So we buy super-expensive inspection machines and reconfigure our assembly lines to accommodate them. We tout their superior GR&R of less than 10%. But when the inspection machine flags a print as bad, we have an operator look at it under the microscope and pass it down the line if it looks good to their “trained eye.”

Seriously? Then why purchase the machine? What’s the point of setting specific inspection parameters on a sophisticated tool, only to overrule them with far coarser and less accurate measurements? I’ve heard a number of reasons for passing flagged prints down the line, but to me they sound more like lame excuses than valid justifications.

When an inspection system fails a test specimen because a measurement does not meet user-defined criteria, I think it is up to the person who set the criteria to investigate why. I’ve spoken with a number of SPI power users, and they all echo similar thoughts on the topic: “When the machine fails prints, it’s trying to tell you that something’s wrong. You have to listen to it and do some engineering to find the root cause.” A few of the gurus shared interesting stories in support of their assertions:

• During the validation testing of a brand new, electroformed stencil, the SPI system flagged half the prints for an odd combination of excessive and insufficient paste volumes. Typical defect modes on these PCBs might be one or the other, but rarely are the modes so mixed. The deposits and apertures looked fine under the microscope, so the engineer measured the stencil thickness in all four corners of the print area. That’s where he found the cause of the variation – a thickness differential of over 0.0025" (that’s 50% of the foil thickness itself!) presumably caused by current density fluctuations during the electroforming process.
• A different assembler found a similar stencil problem when firing up a new product on his line. The print volumes on one QFP kept reading high, but the prints themselves looked great: nice bricks with straight sides and flat tops – no peaks, dog ears, strings, or other visual indicators of excessive paste. A series of measurements revealed that the stencil supplier had mistakenly cut a 0.006" foil instead the 0.005" that had been ordered. Had the engineer simply permitted the visual assessment to override the machine’s measurement without investigation, that stencil would have been placed into production, and would have likely caused lower yields due to suboptimal solder volumes; small features would have gotten less solder than they needed due to decreased area ratios, and larger features would have experienced more bridging due to the excessive volumes and slumping. The resulting yield hit would likely only be a couple percentage points. It could have flown under the radar for a long time, given that this was a new product and there was no baseline for comparison.
• Another series of excessive volume readings – not necessarily rejects, but readings consistently in the 130% range – led engineers at a third assembler to measure the stencils and PCBs. They found the PCB pads were overetched by nearly 0.002", barely meeting the minimum size specification. But the pads met the spec, so the PCBs could not be rejected for quality reasons. The stencil apertures were already cropped for fine-pitch devices, so the size mismatch was about 0.001" – just enough to cause minor gasketing problems and permit excess paste to pump out along the gap. Understanding both the root cause and the degree of risk associated with running higher paste volumes, the engineers decided to open the upper tolerance limit for the remainder of the PCB lot. While I don’t normally advocate opening inspection tolerances to eliminate “false” calls (not truly false calls – just the ones that would be foolishly overridden anyway), in specific cases like this, it makes perfect sense. In fact, that’s why we like our tolerances to be programmable in the first place.

Three different PCB assemblers, three different stories on why we should listen to what our SPI systems are trying to tell us, and in all three cases, a little engineering legwork found the root cause of the problems. Interestingly, in all three cases, the printer and paste were working just fine.

Stencil printing is not just about the printer and the paste; if it were, the process would be a whole lot easier to manage. It’s about the entire system, including PCBs, stencils and squeegees (or print heads), and it’s the systemic interactions that make the process complicated, interesting and fun.

Next time the SPI flags bad prints, don’t pass them down the line with the assumption that the printer is fine. It probably is. While the SPI machine can’t tell you exactly what is wrong in the print system, it can tell you that something is wrong, and it’s up to you to listen to it, identify the root cause, and try to prevent the problem from happening again. After all, that is what process engineers get paid to do, isn’t it?

Chrys Shea is founder of Shea Engineering Services (sheaengineering.com); chrys@sheaengineering.com. She wrote this article on behalf of Christopher Associates (christopherweb.com).