Board Fabrication

“Development of Optical Interconnects with Polymer Waveguides for High-Speed Electronic Systems”
Author: Marika Immonen; marika.immonen@meadvillegroup.com.
Abstract: This paper describes the fabrication and characterization of optical/electrical printed circuit boards (O/E-PCB) with embedded polymer waveguides for 3D optical interconnects. Optical circuitry is built up on PCBs using UV lithography; 45° input/output (I/O) couplers are fabricated by inclined exposure. Commercial polymers are used as optical core and cladding materials. Critical mirror properties of angle, surface quality, reflectivity and coupling efficiency are characterized. (HKPCA, December 2011)

“Wrap Plating for Blind and Buried Vias”
Author: Dale Lovell; dalel@innovative-circuits.com.
Abstract: Wrap plating is a manufacturing step for producing blind and buried vias in printed circuit boards. Wrap plating helps increase via-in-pad reliability by depositing copper in the via hole and around the surface foil. This presentation describes the process, and includes certain aspects of bare board processing, such as innerlayer etching, plasma, layup, laminating, drilling, planerizing, tin strip, immersion gold, soldermask and button (spot) plating. (Printed Circuit University, August 2011)

Component Packaging

“Evaluation of Reliability and Stack-Up Height on Next-Generation 0.5 Mm Pitch PoP”
Authors: Mark Schwarz, Alan Choi, and Owen Fay; mschwarz@qualcomm.com.
Abstract: There is a push from the end-user to make the package-on-package (PoP) stack-up thinner. The overall height of the tallest package mounted on the PCB, often the PoP, becomes the major factor that dictates product design thickness. This paper explores different configurations of the bottom PoP component, while holding the memory component constant. The lower package is 14mm in size, uses a 0.4mm bottom pitch with 904 solderballs. The top package is also 14mm, with a 0.5mm pitch with 240 solderballs. The interconnect between the packages is joined through soldered connections embedded within vias of the bottom package’s mold compound. Three bottom solderball diameters were characterized as a drop-in solution to decreasing overall package thickness. Selected package configurations were evaluated based on drop shock, thermal cycling and cyclic bend reliability test, focusing on both the bottom and top PoP interface. Two mold compound via dimensions and two topball solder alloy compositions were studied for their effects on total collapsed height and reliability. Coplanarity and high-temperature warpage for the various configurations were also monitored. (SMTA International, October 2011)

PCB Design

“Conquering High Pin-Count Devices with Fan-Out and Escape Routing”
Author: Andy Buja; andy.buja@zuken.com.
Abstract: Consumer electronics is highly driven by more features in the same or smaller packaging. As a result, designs have an increasing number of high pin-count devices. Many of these are configurable FPGA devices. Less real estate is available to route these devices, and routing of these components is key to design completion. This presentation focuses on available tools to optimize this process. (ZDAC, November 2011)

“Why DfM?”
Author: Darren Hitchcock; darren.hitchcock@multek.com.
Abstract: Valuable tips on designing printed circuit boards with the manufacturer in mind. Explains how to design PCBs cost-effectively using existing manufacturing processes and equipment. Also includes helpful tips on improving quality, yield and performance, and reducing lead time. (Printed Circuit University, November 2011)

This column provides abstracts from recent industry conferences and company white papers. Our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.