ScanWorks v. 4.8 JTAG-based hardware debug, validation and test tools are for testing device interconnects between silicon chiplets in multi-die packages.

Shorten time to program flash memories. Can now generate test patterns in standard test interface language; can be applied by chip-level automatic test equipment to test for shorts and opens between chiplets. Has greater integration of ScanWorks FPGA-based flash programming. FFP’s embedded test generator is implemented within design module. FFP reduces programming times for flash memory devices. Once small test/programming agent is embedded into on-chip RAM memory of on-board system-on-a-chip, processor-based functional test/programming tool performs fast programming routines, runs functional tests on devices and I/O buses on PCB, and configures or tests DDR memories. Additional devices can be placed on same boundary-scan chain that connects SoC to ScanWorks.

Asset InterTech
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