ARLINGTON, VA – JEDEC Solid State Technology Association announced a broad spectrum of ongoing standards development work related to 3D-ICs. 

The Solid State Memories Committee (JC-42) has been working since June 2008 on definitions of standardized 3D memory stacks for DDR3. The DDR4 standard will be implemented with 3D support from the start.

The Multiple Chip Packages Committee (JC-63) is currently developing mixed technology pad sequence and device package standards. An active Task Group of the Low Power Memories Subcommittee (JC-42.6) is developing standards for wide I/O mobile memory with TSV interconnect stacked on system on a chip application processors.

The Silicon Devices Reliability Qualification and Monitoring Subcommittee (JC-14.3) has been working on reliability interactions of 3D stacks and has released JEP158: 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Understanding and Evaluating Reliability Interactions.  In addition, reliability test methods developed by JC-14.1 and JC-14.2 and quality documents developed by JC-14.4 are applicable to 3D-IC packaged and unpackaged evaluations and qualifications.