SAN JOSE – The SMTA announced the keynotes for its 13th Annual International Wafer-Level Packaging Conference in October.

On Oct. 18, Klaus-Dieter Lang, Ph.D., of Fraunhofer IZM, will present Advanced Technology Platforms for Next Generation of Smart Systems. Presentation topics include application conditions, integration technologies and reliability aspects for smart electronic systems. Examples from wearables, communication and production will illustrate the advantages of their use.

On Oct. 19, Georgia Tech engineering professor Rao R. Tummala, Ph.D., will deliver the keynote, titled Promise and Future of Embedding and Fan-Out Technologies. According to Tummala, all packaging technologies can be classified into two types. Wafer-level packaging is one approach, with ICs built directly into packages in the wafer fab by redistributing the BEOL I/Os and placing bumps. This is the best package electrically, but is limited to small ICs and to small packages – typically below 5mm. As such, it is limited in external I/Os to connect to the board, typically at 400 microns and above in pitch.

To eliminate the I/O limitation issue, fan-out technology was initially developed in the 1980s and more recently further developed into production by Infineon. But this technology is not a wafer-level packaging, as described above; it is not a continuum of transistors to bumps. It did, however, address the I/O limitation. It is primarily an embedded packaging technology called eWLP that permitted fan-out of I/Os, in contrast to WLP, but also enabled embedding to reduce package thickness. This presentation will describe the promise and future of embedding and fan-out technologies.

The annual conference runs Oct. 18-20 in San Jose. For more information, visit iwlpc.com.