Cerritos, CA -- Corelis and Mentor Graphics will host a half-day JTAG seminar in Richardson, TX on Wednesday, April 5. 
 
Topics will include:
Introduction to boundary-scan technology;
Board interconnect testing using boundary-scan;
In-system programming (ISP) of CPLDs, FPGAs and Flash memories;
Automating boundary-scan insertion into ASICs, ICs and cores;
Typical design flow;
Value of automation with BSDArchitect;
Components of boundary-scan insertion;
Integration with other on-chip test methodologies such as scan and MBIST;
Integration with board-level test methodologies.
 
The seminar is free and intended for ASIC designers, board designers, test engineers and managers who would like to understand JTAG test methodologies.  Previous knowledge of boundary-scan technology is not required.
 
For more information and to register, visit: www.corelis.com/Dallas_Seminar_Invite.htm