Methods for 100% test coverage at the assembly level.

While Lean manufacturing strategy is discussed in relation to test strategy, it often focuses on defect mitigation strategies such as integrating program, pack and test activities to minimize variation and transport. However, a Lean manufacturing philosophy can provide even better guidance as companies navigate test strategy options. There is one hurdle to overcome. Google the question, “Is test a value-added activity?” You will see answers in Lean manufacturing forums that range from “if the process is in control you don’t need to test” to “yes, if the customer is willing to pay for it.”

The reality is that in the electronics industry there are very real reasons robust inspection and test strategies are necessary. And, when the cost of field failures is fully considered, a robust inspection and test strategy eliminates much non-valued-added cost. One of the reasons 3-D solder paste inspection (SPI) has gained in popularity is companies have come to understand that  the quality of solder paste disposition has a huge impact on whether there are workmanship-related defects later in the process. Screen for variations at that point, and a large percentage of potential defects are eliminated before components are attached to the PCB. Similarly, in-process inspection by automated optical inspection (AOI) and x-ray help screen out workmanship defects before product gets to test. In fact, the argument that a production line with tight process control and a series of inline inspections won’t generate workmanship-related defects is valid and is often used to justify little or no additional testing between the electronics contract manufacturer and the customer in outsourcing scenarios. The fallacy with that argument is it presumes that PCBAs are populated with 100% known good components. The reality is that while component quality has improved immeasurably since the days when contract manufacturers performed 100% component screening in incoming inspection, the rigors of shipment and high-temperature processing do create bad components. Legacy products have even higher risks in this area, since they often use aging component inventories.

Just as SPI helps reduce board-level rework and scrap early in the assembly process, board-level test helps eliminate higher level assembly rework prior to that assembly process. Additionally, when the cost of shipping and handling a defective PCBA is considered, the sins of overtransporting and overprocessing are put into the mix.  

Consequently, the question becomes, What is the most cost-effective sequence of board-level testing? This is the point where the conversation often turns to design constraints and the cost of fixturing. If a Lean perspective is taken, this question should focus on process throughput rather than cost of fixturing.

Assuming a PCBA can be designed with 100% coverage, in-circuit testing (ICT) will provide the best throughput. When product design engineers collaborate with test engineers to design in the needed accessibility and built-in test capability, ICT can be exploited to reduce the complexity or even the need for functional testing and/or added component accelerated lifecycle testing.

While ICT is typically seen as an electrical test, it can do a much wider range of diagnostic testing, including:

1. Memory testing.

• 0000
• FFFF
• A0A0
• 0A0A
• Walk across 0 to check shorts and opens for data and address lines
• Walk across 1 to check shorts and opens for data and address lines

2. Vector tests when boundary scan devices are incorporated.

• Read the device identification (ID)
• Exercise each vector, including testing for stuck @ 0 and stuck @ 1

The challenge is determining if the available PCBA real estate can provide the required level of accessibility. From a design for testability (DfT) perspective:

• Each single connection should be terminated either pull up or pull down, depending on the internal ICs. When terminated correctly, the circuit performs better, and there is less electrical noise during ICT.
• Even with multiple connections on the circuits, PCB layouts have very poor test accessibility if the PCB layout designer does not provide accessible vias. Unless the product incorporates RF or high-speed technology, the designer should bring all multiple connections to test vias that are accessible from the bottom side of the PCBA.
• The design challenge in providing test vias is that vias under pads can cause solder wicking, resulting in insufficient solder joints, making it imperative to have good spacing for test vias. Solder mask design must also account for accessibility of the test via. Ideally, test vias should be exposed up to 22-25 mils for test access.

In cases where ICT test coverage is below 80%, evaluate different strategies. On a medium-sized PCBA with 650 components, 80% coverage can translate to over 100 untested components. While functional testing alone will detect some issues, it may not detect a component near failure and often isn’t precise in identifying root cause. A combination of flying probe, functional testing and burn-in/accelerated life testing (ALT) may be the solution, particularly when flying probe’s ability to measure component voltage is utilized.

In analog and digital components and bipolar transistors, a flying probe tester can detect the device voltage and determine if the device has issues based on the voltage it detects. Mosfet devices can also be detected this way. However, the voltage measurement is higher. With CMOS or a logic gate, the voltage of the interior transistors can be measured. Since BGAs are digital devices, their tests are different. In these cases, the capacitance value of the logic array is measured and compared to the standard. These tests can be conducted regardless of accessibility. If the layout is dense, the PCBA may be probed down to 10-15 mils for this testing. While flying probe is much slower than ICT from a throughput standpoint, it represents a faster option for detecting bad components than burn-in or ALT. A complex functional test can easily cost $100,000 to develop, so evaluating initial pre-functional test screening options may save money. This type of testing also saves rework time and money, since flying probe will identify the component failure more precisely.

From a Lean perspective, early collaboration among design engineers at the OEM and test engineers in manufacturing will result in a lower cost, more efficient test process. ICT will offer the best cost and throughput if product volumes and test coverage justify it. When they don’t, analyzing the mix of other test options for the best throughput and cost aligned with desired yields is a good strategy. All analysis should consider the cost of failures downstream in the process.

Andrew Vo is director of manufacturing & test engineering at SigmaTron International’s (sigmatronintl.com) Union City, CA facility; andrew.vo@sigmatronintl.com.