News

A model for calculating savings from reduced DPMO against equipment investment costs.

Automated x-ray inspection (AXI) and automated optical inspection (AOI) have the potential to provide substantial savings by reducing downstream electrical testing costs as well as field failures and returns, yet their substantial costs must also be considered. Here we present a method for modeling the economic impact of adding AOI or AXI. The model clearly demonstrates that the economic benefits of either technology depend upon the board complexity, throughput, labor costs, cost of field failures and returns, and equipment performance, as well as capital equipment, programming and operating costs.

Electrical access is shrinking. The average density of PCBs is rising at a rapid pace, making it difficult or even impossible to make room for test points on many boards. The International Electronics Manufacturing Initiative (iNEMI) has reported that electrical access is usually lost somewhere between 25 and 5O I/Os per sq. cm.¹ Some products have reached this range and nearly all will be within it by 2007. Higher frequencies are also restricting electrical access because in-circuit testing of signal integrity and accurate measurements tend to become problematic at frequencies above 500 MHz, where clocks for processors, high-speed memory buses, and high-speed serial communications paths often cannot be tested electrically.

AOI or AXI are looked at to fill the gap caused by reductions in electrical testing access. AOI offers the advantage of being relatively low in cost and easy to use and set up. This method is also capable of easily finding certain fault classes – such as missing electrical and mechanical devices and cosmetic defects. AOI can be positioned at a variety of locations, such as paste, pre- and post-reflow. But the visual access of AOI is being hampered by the shift to area-array packaging, which is in turn being driven by greater board density. Area arrays make up 60% of all ICs², a number that is expected to continue to grow. Greater use of radio frequency shields and heatsinks on top of devices further restricts optical access. Finally, AOI is bumping up against more stringent quality standards such as emerging requirements to detect voids and to measure the full shape and volume of solder joints, especially in Pb-free manufacturing environments.

AXI is able to overcome many of these limitations primarily because it is not affected by reductions in electrical and optical access. AXI detects voids, solder quality defects, hidden joints, and numerous V_CC and GND pins that are invisible to both AOI and ICT. Improvements in AXI systems in recent years have provided the ability to acquire angled images needed for 3D inspection without mechanical movement of the source and detector. This approach provides an unobstructed view of nearly every component, improves image quality – particularly edge definition – and delivers a large field-of-view with the resolution needed to inspect 0201s. The technical advantages of AXI must be weighed against a capital cost that is higher than AOI systems.

Different Workflow Models

Before providing a method for analyzing the economics of AXI, it’s important to note that AXI and AOI have different workflow models than ICT, functional test (FT) and system test. Electrical test is a closed-loop process in which the device is electrically tested. Rejected parts are diagnosed and repaired, and then the board goes through the test cycle again. If the board fails a second time, it can be repaired and tested again, although there is a limit on the number of times the test and repair cycle can be repeated before the board is rejected.

Figure 1 shows the different workflows of AXI and AOI during which the board is inspected, then debugged and repaired, and then passed on to the next process, typically ICT, without further inspection. This is because a manual solder joint produced during the repair process is so different from one produced in a reflow oven that it cannot be reliably inspected by AOI or AXI.

Because AXI and AOI are open-loop processes, it’s important to consider the effects of operator analysis and verification on their performance. Operators are not infallible, and so it is necessary to assume some level of error during analysis and verification. A typical level, which we will assume in the following analysis, is that operators correctly label 90% of actual defects as real and incorrectly label 10% as false. That 10% then escapes to ICT. Operators also label 98% of false defects as false and 2% as real defects, which generate unnecessary repairs. Indeed, some independent studies have shown that in a high-volume environment where the number of false defects can be high, the actual percentage of false calls wrongly verified can be as much as 50%.³

Now let’s look at the capabilities of each test and inspection process. Figure 2 shows the test access, fault coverage, and false fail rate of typical AXI, AOI and electrical test systems. The test access is the level of physical access that an inspection or test stage has to the PCB. Fault coverage refers to the effectiveness of a test stage in detecting a specific defect type on a location that is fully accessible. The test coverage is the product of fault coverage and test access. Note that AXI has considerably greater test access than AOI because it is not subject to the loss of optical access resulting from the increasing use of area-array products. The fault coverage for AXI and AOI are essentially the same, yielding a significant advantage for AXI in overall test coverage (87% to AOI’s 66%) in this application.

The false-fail rate has a major impact on ROI when adding an inspection system. The latest 3D AXI systems have comparatively lower numbers of false failures because of their large field of view, sharper images and increased number of gray levels. Subject to the limitations of 2D optical access, AOI systems typically have a significantly higher false fail rate. For the same reasons, operators using 3D AXI systems typically achieve slightly better verification performance.

Figure 3 shows the parameters of a typical application that we will use to demonstrate the ROI model. The example is based on the labor rate faced by a typical medium-volume North American or European assembler. It shows the costs involved in different phases of the testing cycle. The costs of verification/diagnosis, repair, and retest increase substantially at each successive stage of the testing cycle. This provides one of the major reasons why AXI or AOI can reduce the overall costs of test. AXI and AOI make it possible to identify and repair defects in the early stages of test and inspection when defects can be diagnosed and repaired at a lower cost. For this example, the annual system costs, including amortizing the capital investment over a five-year period plus operations and maintenance, is $110,000 for AXI and $30,000 for AOI.

Figure 3 provides information needed to calculate the test and inspection-related costs of three alternative approaches: 1) electrical test only without AXI or AXO, 2) AOI plus electrical test, and 3) AXI plus electrical test. Table 1 shows the costs for the first alternative, electrical test only. The total test-related costs, including verification, repairs, component scrap, PCB scrap, retest, and field failures and returns is calculated by the model at $1,311,567.

Table 2 shows how the model calculated costs for AOI plus electrical test using the same assumptions. Note that the addition of AOI has added some substantial costs, including the cost of the equipment, programming, dealing with false calls and false repairs, plus the annual cost of verification, repair and component scrap at the inspection stage. The addition of the AOI provides downstream savings that are substantially greater than its upfront costs because faults can be dealt with at a lower cost earlier in the inspection and test process. Furthermore, the number of escapes is substantially reduced, which reduces the cost of field failures and returns. The net result is that the overall test and inspection-related costs are reduced by $310,587, a 24% reduction from the base case.

Table 3 shows the costs calculated by the model for the third case, AXI plus electrical testing. This case also shows substantial additional costs for purchasing, operating, maintaining and programming the AXI system; false calls and false repairs at the inspection stage; and verification, repair and component scrap at the AXI stage. The total AXI costs in this case amount to $623,627. Yet AXI also provides larger benefits than AOI in this example, primarily because its higher test access and lower false failure rate leaves fewer defects that need to be addressed during electrical test. In this case, AXI reduces the defects per million opportunities remaining in the board prior to ICT from 242 ppm in the base case to 43.4 ppm, which lowers the total cost of downstream processes by $1,092,820. The net effect is that adding AXI saves $440,105 per year compared to electrical test alone, an advantage of $129,518 per year over AOI.

The model described here can be used to examine the impact of adding AOI or AXI to any PCB assembly process as long as the required input information mentioned above is available. Repeated applications of the model demonstrate that the advantages of AXI rise with increasing board complexity and fall with reduced board complexity. For example, when the joint count is increased to 6,000, the number of devices to 550, and the number of hidden joints to 1,800 balls, yielding AOI access of 70%, AXI provides a $228,015 per year advantage over AOI and a $674,457 per year advantage over electrical test alone. On the other hand, when the joint count is reduced to 1,000, the number of devices to 400, and the number of hidden joints to 500, yielding 88% AOI access, AXI’s advantage over AOI is reduced to $57,590.

References

1. International Electronics Manufacturing Initiative, 2004 Roadmap.

2. Electronics Trends Publications Inc. The Worldwide IC Packaging Market, 2006 Edition, April 2006.

3. David M. Mendez, “Development of an Integrated Overlapping ICT and X-Ray Process,” IPC Apex Proceedings, January 2001.

Keith Fairchild is northern region sales manager at Teradyne Assembly Test Division (teradyne.com); keith.fairchild@teradyne.com.