Flip chip SiP has five fewer processing steps, among other benefits.

As operating frequencies increased, the traditional wirebond package became a limiting factor in performance for large devices. At the same time, chip designers found it harder to create high first-pass-yield silicon devices containing millions of transistors, and embedded passives for system-on-chip (SOC) radio transceivers. This opened the door for system-in-package applications (SiP). SiP integrates surface mount components and silicon devices on a package substrate. SiP started out as a bridge technology to be used between device generations. However, many companies exist today by making SiP devices or “modules.”

As packaging subcontractors geared up for the increase of SiP applications, device designers kept pushing on SOC solutions as well. To keep pace with SOC package size reductions, SiP implementations went from packaged devices integrated with passives, to chip-on-board with wirebonds and passive surface mount devices. Today many radio transceivers use flip chip because wirebonding requires up to 0.75 mm of clean space on each side of the device. However, flip chip has some issues. Most low to moderate (<100 I/O) pin count devices use a metal leadframe substrate. This results in a low cost-per-pin package. The metal leadframe is the package of choice for radio chips. Conversely, flip-chip devices are packaged on a laminate board. The laminate could be FR-4, polyimide, bismaleimide triazine (BT), Duroid, or liquid crystal polymer (LCP). These materials all have mechanical and electrical properties suitable for use in various applications.

In a standard leadframe package, a large metal pad is used as the attachment point for the device. In the past, devices were grounded through the backside of the silicon, but patent protection, “latch-up” issues and the desire to have separate grounding schemes on one piece of silicon have led most companies to ground devices from pads on the device’s top side.

Leadframe packages with short wires to ground have about 0.1 nH of inductance to ground. A laminate package with one via to ground and a routed line in the laminate may have 0.5-0.8 nH or more of inductance. This difference in inductance to ground is not trivial. Radio transceiver performance at moderate to high frequencies can be diminished by this difference. To mitigate this, the use of a land grid array package is an excellent choice.

When a device is flipped onto an LGA, one of the central four pads can be used as a ground pad. By patterning vias to one of the quad pads that lie under the flip-chip ground pad connections, the inductance to ground can be lowered to match the inductance of the metal leadframe. If EMI is an issue, a drop-in shield can be added before injection molding.

When RF devices go flip chip, a change in the values for components that comprise the radio device is necessary. Typical components for a front-end module include (but are not limited to) band and low pass filtersand baluns. Combinations of capacitors and inductors create these circuits. Filters are designed using the packaged radio devices’ characteristic impedances and capacitances. An EM simulation tool is used to determine the values of inductors and capacitors required to create the passive networks. Tradeoffs are studied by making slight changes to inductance and capacitance values until the simulation reaches optimum performance. Passive components are provided with tolerance ranges of 1 to 5% or more. Using components with a wide tolerance such as 10 or 20% will lower the component cost. However, the resultant values for capacitance and inductance will vary, and combinations of wide tolerance components may produce a filter that does not perform adequately in the field. Another simulation that examines variability and relates it to performance over multiple components with varying values is known as a Monte Carlo simulation. This simulation, made at the conclusion of the EM simulations, determines the effects of component variation. This ensures the selected component tolerance will create performance that is suitable for the applications of the product.

When a leadframe and wirebonds are replaced by flip chip and laminate, device characteristics change enough to require alterations to filters and passive networks. Acquiring the flip-chip device characteristics requires use of a flip-chip test bed and network analyzer to measure device impedance during operation.

One advantage of migrating to flip chip from a wirebonded SiP is the fewer number of processing steps. Traditional wirebonding with surface mount passives involves a 15-step product flow (Figure 1). The process for SiP with flip chip (Figure 2) has just 10. Making all attachments by soldering clearly reduces the number of process steps required to create the final product.


With SiP modules, the most difficult part of the RF integration happens inside the package. A company wishing to use the module need only develop a 50Ω (or other, depending on the device) impedance transmission line to the antenna input. Conversely, the same company selling a single chip may spend many days helping prospective customers debug product boards to get optimum performance. From a time-to-market perspective, modules ease integration headaches, reduce board problems and lower cost at market entry.

The American Competitiveness Institute (aciusa.org) is a scientific research corporation dedicated to the advancement of electronics manufacturing processes and materials for the Department of Defense and industry. This column appears monthly.