ECTC Boasts Record Crowds, FO-WLP Sessions Overflow
Whether round or rectangle, HDI will be required to meet the needs of next-generation semiconductor nodes.
The IEEE Electronics Components and Technology Conference (ECTC) welcomed a record crowd of more than 1,700 attendees to San Diego to discuss the latest trends in packaging and assembly.
For the second consecutive year, fan-out wafer level (FO-WLP) packaging sessions reached overflow capacity as attendees streamed in to hear the latest developments. Regardless of format, round or rectangle, high-density interconnect will be required to meet the needs of next-generation semiconductor nodes – 7nm coming soon and 5nm to follow. Die-to-die and die-to-high bandwidth (HBM) memory stack (as described by Nvidia) requires high density interconnect. MediaTek announced its INFO (M-Link), a die-to-die networking solution using TSMC’s InFO on substrate process, and provided reliability data and signal and power integrity analysis.
Many presentations described efforts to obtain finer feature sizes. TSMC discussed a new submicron polymer redistribution layer (RDL) technology for its InFO package. Atotech, Dow and others described plating developments, while equipment companies including Applied Materials, Rudolph, SPTS, Suss Microtec, TEL NEXX, ULVAC, Yield Engineering Systems and Disco introduced improved process solutions. Rudolph and Ultrasonic Systems discussed a new lithography system with a novel nozzleless spray coating technology. New material developments for FO-WLP from Brewer Science, FujiFilm, Hitachi Chemical, Lintec and Nagase ChemteX were also presented.
TSMC’s expanded Integrated Fan-Out WLP (InFO-WLP) platform extends to more than application processors, with stacking options and a version that incorporates an antenna in the package called InFO_AiP. IME described research on an antenna in a FO-WLP. The antenna-in-package options are increasingly important for mmWave applications including 5G, but FO is not the only option. ASE, SPIL, NCAP, Georgia Tech, IBM and Toshiba presented developments in other package options incorporating antennae.
Large-area panel processing attracted tremendous attention as a potential cost-reduction measure. Nepes presented its panel development, with a fingerprint sensor as the first product. Samsung Electro-Mechanics (SEMCO) detailed its chip-first FO panel with 2µm lines and spaces. Researchers found less warpage with a glass carrier than organic carriers. Panel yield will be critical to obtain the economic advantages. Researchers from Fraunhofer IZM and TU Berlin described the latest developments from their consortium and provided a realistic assessment of large-area processing issues and opportunities for research to move the technology forward. Several presentations from the consortium led by ASM Pacific Technology (with members Unimicron, JCAP, Dow, Huawei, Indium and Hong Kong S&T), described developments on panel processing.
Consortia such as ITRI, IME A*Star, Korea Advanced Institute of Science and Technology (KAIST), Ncap, Imec, along with companies including Amkor, ASE, Huatian, MediaTek, NANIUM, SPIL, and Stats ChipPac also discussed advances with FO-WLP. ASE compared electrical performance of eWLB, M-Series, and a chip-last approach.
New FO-WLP panel consortia launched. A new consortia organized by Hitachi Chemical called Jisso Open Innovation of Tops (JOINT) was unveiled for the first time at ECTC. Members include AGC Asahi Glass, Disco, JSR, Lintec, Namics, Mitsui Kinzoku, TOK, Toray Engineering, TOWA, Uyemura and Ulvac. Unimicron joined the consortia during the conference. The material and equipment vendors are coming together to advance the large area technology using an RDL-first fan-out test vehicle design by Hitachi Chemical. The 24 sq. mm package, fabricated on a 320mm square panel features a four-layer RDL with 2µm minimum line and space. Eight chips are mounted with a minimum bump pitch of 40µm. Canon’s stepper will be used, with a large-area flip-chip bonder from Toray Engineering used to bond the chips. TOK will provide photoresist and Uyemura will provide the copper electroplating solution. Ulvac’s sputtering system, Shikoku’s OSP, and Mitsui Kinzoku’s glass carrier will be used. Hitachi Chemical will provide dielectric, mold compound and underfill for the first test vehicle.
Artificial intelligence. AI and its impact on system design was the subject of a plenary session that featured presentations from GlobalFoundries, IBM, Microsoft, Georgia Tech and Samsung. A keynote lunch speaker from Broadcom described packaging advancements to enable AI, with applications ranging from autonomous cars to wearables.
In an evening session on high-density packaging technologies in the era of big data, speakers from Fujitsu, IBM Research, JCET, Stats ChipPac, Shinko Electric, and Hitachi Chemical discussed some of the packages required.
Silicon interposers with through-silicon via (TSV) are now mature products for high-performance applications, as indicated in several presentations. Xilinx provided a comprehensive study on package design for board-level reliability in thermal cycling and power cycling for its silicon interposer with package. Nvidia described a micro-bump system for its second-generation GPU and HBM on a silicon interposer.
Wafer-to-wafer bonding. Wafer-to-wafer (W2W) bonding is a hot topic, especially with TSMC’s announcement of its W2W bonding this spring. IMEC presented its failure analysis for 1.8[U]m pitch wafer-to-wafer bonding. The Institute of Microelectronics and Tsinghua University discussed a low-temperature fine-pitch wafer-level Cu-Cu bonding using PVD fabricated nanoparticles. National Taiwan University and the Joining and Welding Institute at Osaka University described a low-temperature Cu-Cu bonding using a microfluidic electroless interconnect process. Xperi described a low-temperature hybrid bonding process to bond interconnect at <20[U]m.
Automotive reliability and power devices. Automotive electronics also remains a hot topic. Reliability requirements are especially important. A presentation from Texas Instruments described corrosion prevention for Cu-wire bonded devices to improve bonding reliability. Intel discussed underfill degradation in packages for ADAS. A presentation from researchers at Georgia Tech focused on high temperature and moisture aging for power packages. A joint presentation from Keio University, Alpha Assembly Solutions/MacDermid clarified the warpage and thermal stress for SiC and Si power devices using a direct Ag sintering clip-attachment on a Cu plate.
Emerging technology. A special session on emerging technologies for medicine, healthcare and human-machine interfaces opened the pre-conference special sessions on Tuesday morning. The focus was on soft materials, processing and manufacturing methods, and the utilization of flexible hybrid electronics for these applications. Speakers from University of Minnesota, University of California, Psyonic and Microtek described the latest developments.
A special session on novel assembly methods to manipulate ultra-thin, small chips with high throughput covered a range of topics from microLED displays to advanced memories. Speakers from Darpa, PlayNitride, Besi, X-Celeprint and Uniqarta provided insight into some of these methods. PlayNitride and X-Celeprint highlighted the potential for microLED assembly.
Additive manufacturing featured a presentation from Texas Instruments that discussed additive printing technology for IoT, 5G and automotive radar applications. CEA-LETI researchers described the use of a 3-D printing encapsulation process. Researchers at Georgia Tech discussed printed electronics for wearable RF antennas, and researchers at ASU discussed printed electrochromic films for wearable electronics.
The importance of co-design. One night session focused on IC and package co-design for heterogeneous integrated systems. Avi-Bar Cohen from Raytheon, the current IEEE EPS president, and Chris Bailey of University of Greenwich led the discussion. Representatives from ASE, Mentor, ON Semiconductor, Lamar University, Georgia Tech and University of California, San Diego highlighted the importance of co-design.
Reliability, sintering pastes, power electronics, nanotechnology, biochemical, optoelectronics with a focus on silicon photonics, advances in wire bonding, materials, flip-chip manufacturing challenges, RF modules, through-silicon via (TSV), and thermal characterization sessions rounded out the program. Several sessions discussed the issue of warpage with wafers, silicon interposers, fan-out WLP, package-on-package (PoP), panel-level fan-out, and laminate substrates including PBGA.
A special session was devoted to emerging packaging technologies for 5G and advanced computing. Several presentations at the conference discussed new material developments for 5G.
Interactive poster sessions allowed in-depth, one-on-one discussions with the authors. Many new exciting developments are often presented in these sessions. These included a 3-D-printed liquid jet impingement cooler from IMEC and KU Leuven, and Smoltek’s integrated fully solid-state capacitor based on carbon nanofibers and dielectrics.
The Heterogeneous Integration Roadmap also held a meeting to continue its roadmap development activities. A special session discussed how to enhance women’s participation in engineering around the globe. Funding for the IEEE Foundation Frances B. Hugle Memorial Scholarship was announced with contributions from 100 individuals and corporations. Bill Chen’s contribution to the scholarship from his IEEE Electronics Packaging Field Award honoring his wife allows the application process for young women in engineering to begin.
Next year, ECTC will be held in Las Vegas May 28-31. The Electronics Packaging Society (EPS) expects another record attendance.
is president of TechSearch International (techsearchinc.com); jan@techsearchinc.com.
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