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A comprehensive DoE finds paste and placement offsets the top contributor to defects.

The mechanics of tombstoning are based on molten solder wetting forces, component mass and geometry. If solder paste under one termination melts and starts wetting to the termination before the other side does, the wetting action force can pull that component up on its end. Typically, the smaller and lighter the component is, the more susceptible it is to tombstoning.

Factors in tombstoning can be classified into two main categories: design-related (pad design; pad definition, mask or metal; thermal balance between pads; unfilled microvias in the pads) and process-related factors (numerous, and often difficult to quantify). Many DoEs have been performed and published on the topic, often focusing on best practices for design and assembly.

Most 0201 assembly processes were optimized prior to the transition to Pb-free processing. Increasing production of Pb-free products and the associated tighter process windows now dictate a reassessment of the key parameters that can affect tombstone formation.

Experimental Design

A review of published studies and high-volume production experiences uncovered 49 potential parameters that can influence tombstone defects. The investigators then used a cause-and-effect (C&E) matrix approach (rating influence 0, 3 or 9) to identify the following 12 parameters as the most influential:

• Padstacks. This includes pad sizes and spacing between pads. All pads were non-solder mask defined (NSMD), and did not have solder mask between the pads. Four sizes were considered. Three are considered public domain; the fourth is considered proprietary.
  
  
• Solder paste volume. Stencil apertures were designed at 70% and 100% area of each pad size. A 70% area represents the least acceptable transfer efficiency; 100% area represents the best possible transfer efficiency. For the feature sizes used in this study, apertures designed at 70% released about 50% of the paste from the apertures, and apertures designed at 100% released about 60%. The transfer efficiencies vary with each solder paste and the different apertures’ area ratios.
  
  
• Print offsets. To simulate alignment error, stencil apertures were designed at nominal pad position and with 0.1 mm offsets in both X and Y directions, for a total of four combinations: (0,0; 0,0.1; 0.1,0.1; and 0.1,0.1).
  
  
• Component type. Resistors and capacitors were used to capture effects of component height and number of sides per termination.
  
  
• Orientation. Components were mounted at 0 and 90°.
  
  
• Reflow profile. Straight ramp and high soak profiles were used.
  
  
• Reflow atmosphere. Air and 100 ppm N2 atmospheres were applied in soldering cycles.
  
  
• Placement offset. Components were placed at two positions: their nominal 0, 0 (CAD) position, and a 0.1, 0.1 mm offset in X and Y concurrently.
  
  
• Solder paste. In Phase 1 of the study, three solder pastes were used: no-clean SnPb, no-clean SAC 305, and water washable SAC 305. In Phase 2, the number of pastes was expanded to seven.
  
  
• PWB final finish. In Phase 1, organic solderability preservative (OSP) was used. In Phase 2, OSP and electroless nickel-immersion gold (ENIG) finishes were used.

The experiment was partitioned into two phases. The experimental matrix for Phase 1 is shown in Table 1. Factors listed in the top half were designed into the test vehicle (Figure 1). Factors in the table’s bottom half were varied during the assembly process.

Test vehicle. The TV contained 48 individual test cells. Four different pad designs were used, each appearing twelve times on the test vehicle, six times per row of cells on two rows. Each cell had 50 resistors and 50 capacitors oriented at 0 and 90°, a total of 200 per block (Figure 2). Eight cells per padstack were assembled per board, for a total of 1600 placements per padstack per board. In Phase 1, all four padstacks were used, resulting in 6400 component placements per board.

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