"Sequential Lamination"

by Stanley L. Bentley, Divsys

Abstract: Sequential lamination is necessary when the design of the interconnect system has connections that are not required on all layers or that if made available on all layers would impact the system performance or create an unsolvable congestion in the design.

Published May 2012

"Copper Foil Weight vs. Thickness"

by Stanley L. Bentley, Divsys

Abstract: The copper foil on the printed circuit board has two very confusing units of measure. These
units are frequently mixed and confused for one another.

Published November 2012

Joint Project for Mechanical Qualification of Next Generation High Density Package-on-Package (PoP) with Through Mold Via Technology

Abstract:
This paper will summarize joint work between ST Microelectronics, Amkor Technology and Nokia; to qualify Amkor’s through mold via (TMV™) bottom package technology for next generation high density PoP applications. The 12 x 12mm daisy chain test vehicle reported in this joint work includes a thin flip chip die in a fully molded bottom package with 516 bottom BGAs at 0.4mm pitch and 168 top solderable through mold vias at 0.5mm pitch. This paper will report the package level (moisture resistance, temperature cycling) and board level (temperature cycle, drop) qualification data against IC and handheld application requirements.

Additional data for package warpage control and board level reliability for larger PoP applications using TMV technology will be included beyond what was reported at ECTC ¹, SMTA International ² during 2008 and IMAPS Device Packaging ³ in March 2009, based on a 14 x 14mm daisy chain test vehicle with 620 bottom BGAs at 0.4mm pitch and 200 top vias at 0.5mm pitch. Additional data on the TMV technology will be provided including: maximum die to package size design benefits for wirebond, stacked and flip chip die, coplanarity and package warpage measured by shadow moiré across lead free SMT reflow profiles. JEDEC standardization work for next generation PoP applications will be provided for mechanical and high density electrical interface requirements driven by low power double data rate 2 memory (LP DDR2), in single and dual channel architectures which require 0.5 and 0.4mm pitch interfaces respectively. ⁴

Assembly and Reliability Assessment of Fine Pitch TMV Package on Package Components

Abstract:
Since their introduction, package on package components have proven popular, particularly in handheld portable applications. These packages offer significant advantages, including increased density through stacking of logic and memory devices in the same component footprint, and flexibility as a result of the assembler’s ability to select different memory devices for inclusion in the stack. Next generation versions of Package on Package devices are now emerging which offer improvements in component warpage during reflow and increased pin count due to pitch reduction on both the top and bottom package. This study focused on different assembly variations for a new 14 mm square package on package component with a 0.4mm pitch array on the lower package and 0.5mm pitch array on the upper package. This configuration allows for 620 I/O on the lower package, and 200 I/O on the upper package. The lower package in the stack featured a through mold via (TMV) structure, which reduces component warpage, and improves assembly yield. Flux Dip and Paste Dip were assessed for assembly of the upper package in terms of assembly yield, mechanical shock and thermal cycling reliability. Two different underfill materials were assessed for use on these components – one selected for optimal shock test performance, and one selected to optimize thermal cycling reliability. All assembly variations were subjected to accelerated thermal cycling (ATC) from -40°C to 125°C with a planned test duration of 2000 cycles. Mechanical shock testing was performed on a sub-set of the assembly variations to complete the reliability assessment.