Circuits Assembly Online Magazine - In Case You Missed It

Flip Chips

“Development of Ultra-Thin Flip Chip Assemblies for Low Profile SiP Applications”
Authors: Charles V. Banda, et al.
Abstract: This paper reports the results of collaborative work done at Johns Hopkins University’s Applied Physics Laboratory, Auburn University’s Laboratory for Electronic Assembly and Packaging and the U.S. Government’s Microelectronics Research Lab to develop processes for the manufacturing of ultra-thin direct chip attach flip chip assemblies using commercial flex substrates. A novel process was developed for the bumping of precision thinned die that allows bumping to be done after the thinning process. In addition, a technique was developed allowing the assembly and underfilling of thinned die without specialized equipment or processes. Die thicknesses down to 25 µm were assembled to flex substrates for this study resulting in paper-thin, 100 µm thick assemblies. (IMAPS International, November 2004)

Lead-Free Reliability

“Manufacturing Optimization and Reliability of Large Soldered Daughter Modules for High Performance Communication Applications”
Authors: R. Scott Priore, Sergio Camerlo, Mark Brillhart; spriore@cisco.com
Abstract: Tests were conducted on a 16-layer, high-TG FR-4 buildup technology (1+14+1) daughtercard, 2.9 x 3.9", 0.080" thick with a BGA ball count of 860. The daughtercard bill of materials incorporated one daisy-chained 40 mm FCBGA, eight daisy-chained FCBGA memory chips and passives. All components were placed topside. The solder balls were 0.35" in diameter using standard tin-lead eutectic solder. Manufacturing optimization was performed for stencil apertures and solder paste volume; standoff of BGA solder joint required to achieve target reliability based on FEA prediction; reflow profile for large body size daughter module; and rework process for a large body size daughter module. Long-term interconnect reliability was also evaluated through extensive thermal cycling (0-100°C, 3500 cycles). (Pan Pacific Microelectronics Symposium, January 2005)

Solder Pastes

“Round Robin Testing and Analysis of Lead-Free Solder Pastes with Alloys of Tin, Silver and Copper, Phase II Down-Select and Assembly Report”
Authors: IPC Solder Products Value Council Lead Free Technical Subcommittee, pcdandm.com/pcdmag/specialreports/
Abstract: Results of testing by Flextronics and Solectron of lead-free solder pastes and a tin-lead control to produce lead-free test assemblies. Criteria used in the assembly process included: test and inspection, rework and repair, solder paste handling and storage, print operations, reflow process and cleaning. Based on the statistical analysis of the assembly data, no significant difference in assembly performance was found between the lead-free solders and tin-lead solder.

Rework

“Hot Air Lead-Free Rework of BGA Packages and Sockets”
Authors: Alan Donaldson and Raiyo Aspandiar; alan.w.donaldson@intel.com
Abstract: Hot air rework profiles were developed for BGA package sizes from 15 to 37.5 mm, soldering on immersion silver, OSP and nickel-gold surface finishes. The BGA package solder balls were Sn/Ag4.0/Cu0.5, attached to electroless nickel immersion gold (ENIG) at the package interface. A hot air rework process for a 478 BGA lead-free socket with two different solder ball compositions (Sn/Ag3.5 and Sn/Ag3.0/Cu0.5) was also developed. The rework temperature range for the packages was 230-250°C. Detailed intermetallic compound analysis was also conducted.

Reliability tests included temperature cycling, static bake, mechanical shock and vibration. A generic guideline for lead-free rework profiling was established based on this study. (SMTAI, September 2004)

Underfill

“Processing and Reliability of No Flow Underfills and the Influence of Underfill Voids”
Author: Dr. Daniel F. Baldwin, dan.baldwin@engentaat.com
Abstract: Current no-flow underfills and their associated processes are often found to void excessively. In an attempt to minimize underfill voiding, the effect of critical substrate features, such as soldermask height, copper trace height and mask/trace separation, have been studied for their effects on underfill voiding for the typical no-flow process. However, substrate design alone cannot eliminate the voiding issues in no-flow underfills. This paper presents a combined materials and processing investigation of the voiding phenomena, ultimately comparing the reliability qualification data of assemblies with and without voids. (IMAPS Device Packaging Conference, March 2005)

Circuits Assembly provides abstracts of papers from recent industry conferences and company white papers. With the amount of information increasing, our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.