Hints for offsetting QFN void formation.

QFNs: Designers love them. Assemblers don’t necessarily share that affection. These very popular devices, first on the electronics scene in the late 90s/early 2000s, have become one of the more popular packages among handheld manufacturers. From a design and manufacturing point of view, the QFN is an excellent package. QFNs are flat, plastic packages with perimeter leads underneath the device (as opposed to leads that extend outside the package) with a large pad in the center. They are low-cost in comparison to other components, allow a high number of I/Os and are an excellent alternative to traditional QFPs, TSOPs and the like.

A QFN’s ability to pack major functionality into a relatively thin package in addition to excellent electrical and thermal performance has driven their popularity. And, since their introduction over a decade ago, these devices have expanded on their functionality capability. Advancement in QFN design has given rise to dual- and even triple-row perimeter I/O, whereas the first designs had only a single perimeter row of I/O. In addition, QFNs are now incorporating other packaging styles such as internal die stacking to increase function.

So, while designers adore the QFN for all of the design latitude, assembly specialists – and to some degree packaging specialists – have many QFN challenges to overcome. At the package level, manufacturing hurdles include issues with wire bonding on polyimide and the die to pad ratio effect on JEDEC performance. New conductive die attach films, however, are helping overcome the die to pad ratio challenge and are also enabling more die per package, as these materials essentially eliminate the fillet associated with paste-based mediums. At the board level, ensuring long-term reliability is the central issue. In truth, what makes the QFN so appealing for component and handheld product designers is at the root of one of its greatest assembly challenges: solder voiding.

The architecture of the QFN makes it inherently more susceptible to void formation. The reduced standoff (which makes these components appealing to designers) combined with the planar surfaces easily traps escaping solvent vapors and activator residues. While the increased cross-section of the interconnect joints compared with a CSP mean that voiding is typically not a reliability issue, the same cannot be said of the central ground plane which is often used as a heat sink. The large central solder paste deposit provides only very limited escape routes for the volatile materials generated during a reflow process, resulting in an increased level of voiding.

The parameters that contribute to QFN voiding are many and varied including the size and design of the device itself, reflow profiles, solder paste capability and multiple other process conditions. And, just as there are multiple factors influencing the formation of QFN voids, there are several approaches to reducing them. One of the more well-established techniques for minimizing voiding is depositing the paste for the center pad in a specific pattern, depending on the size of the QFN. Arguably the most popular of these is the windowpane pattern where the pad is divided into between four and 16 equally-sized smaller deposits (Figure 1). Although these patterns are well-used, little work has been done on the efficacy of any one design. The ratio of total pad area to deposit area becomes more important as the number of panes increases and it is crucial not to starve the pad of solder as this can cause an increase in voiding. This approach can reduce the voiding from around 35% for a single large deposit down to below 20%.

The paste pattern is important, but even more critical is a complete understanding of the characteristics and capability of the flux medium formulation within the solder paste and, to some degree, the alloy construction. Partnering with a materials supplier that has expertise in flux development and can test flux performance in-process prior to material commercialization ensures success. Over the past few years, major advances in flux formulation technology have been achieved and this evolution in flux design is benefitting QFNs and other large planar pad devices in terms of overall performance – including the reduction of voids.

The simple fact is that a complete understanding of the role and interaction of the various flux components and their ultimate impact on the performance of the final paste is essential to optimize product performance. A supplier’s formulation expertise and application knowledge regarding the acids, bases, rosins, activators, alloys and other flux components enables the development of high performance fluxes and solder pastes. In fact, newer generation solder pastes have shown as much as a 10% to 15% reduction in the base QFN voiding as compared to older generation pastes and this is due in large part to the evolution of flux design techniques. That said, each process, each environment and each assembly is unique and, therefore, takes a customized approach to delivering high yields and high reliability. It’s not only flux formulations that impact voiding; it’s also other paste characteristics such as rheology during reflow that enable voids to escape more easily.

There are multiple factors that affect QFN void formation including the flux, alloy, reflow, component type and board metallization, to name a few. Without question, flux is a huge variable when it comes to voids but it has to be balanced with all of the other factors as well. My advice? Start with robust flux formulations, understand each customer’s unique process conditions, delve into the specific application and then develop a solution that achieves the desired QFN result: less voids and higher reliability.

Acknowledgements

The author would like to thank technical service supervisor Jonathan Jiang of Henkel for his valuable input.

Jie Bai is a chemist at Henkel Electronics Group (henkel.com); jie.bai@us.henkel.com.

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