News
NORCROSS, GA -- Assembléon, the supplier of placement machines, named Leo van de Vall president and chief executive of Assembléon Americas Inc. He replaces Michael Buscher, who founded the American branch several years ago.
The move is effective today. He is based in the company's office outside Atlanta.
The move is effective today. He is based in the company's office outside Atlanta.
HIALEAH, FL -- Electronics contract manufacturer Simclar Inc. reported 2005 revenue of $61.2 million, up 14% from 2004. The net income was $1.3 million, compared to $2.3 million in 2004.
Much of the revenue gain -- 55% -- came via acquisitions; year-on-year sales of preexisting business units rose 6.5%.
Much of the revenue gain -- 55% -- came via acquisitions; year-on-year sales of preexisting business units rose 6.5%.
Cerritos, CA -- Corelis and Mentor Graphics will host a half-day JTAG seminar in Richardson, TX on Wednesday, April 5.
Topics will include:
Introduction to boundary-scan technology;
Board interconnect testing using boundary-scan;
In-system programming (ISP) of CPLDs, FPGAs and Flash memories;
Automating boundary-scan insertion into ASICs, ICs and cores;
Typical design flow;
Value of automation with BSDArchitect;
Components of boundary-scan insertion;
Integration with other on-chip test methodologies such as scan and MBIST;
Integration with board-level test methodologies.
The seminar is free and intended for ASIC designers, board designers, test engineers and managers who would like to understand JTAG test methodologies. Previous knowledge of boundary-scan technology is not required.
For more information and to register, visit: www.corelis.com/Dallas_Seminar_Invite.htm
Topics will include:
Introduction to boundary-scan technology;
Board interconnect testing using boundary-scan;
In-system programming (ISP) of CPLDs, FPGAs and Flash memories;
Automating boundary-scan insertion into ASICs, ICs and cores;
Typical design flow;
Value of automation with BSDArchitect;
Components of boundary-scan insertion;
Integration with other on-chip test methodologies such as scan and MBIST;
Integration with board-level test methodologies.
The seminar is free and intended for ASIC designers, board designers, test engineers and managers who would like to understand JTAG test methodologies. Previous knowledge of boundary-scan technology is not required.
For more information and to register, visit: www.corelis.com/Dallas_Seminar_Invite.htm
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