A 0.003˝ stencil provided better paste transfer for miniature passives.

Ed.: Part 1 (in July) summarized the study. Here, the findings are revealed.

Presenting the detailed results and analysis for the current study is beyond the scope of this column. Hence, results from selected areas, representing the board design, are presented here. The test samples contained miniature components such as 01005s and 0201s, and larger components with varied aperture sizes, such as 0402s, QFP 160s and TSOP32s. As the primary goal of the printing experiment was to understand the relationship between board finish, stencil technologies and stencil thickness, only the pad-to-aperture ratio of 1:1 data is presented.

Data analysis. Variability plots for QFP160 and 0201 using the laser-cut stencil DOE showed that with the larger aperture size, absolute volume deposited increases steadily, as expected. We also observed the sample-to-sample measurement is quite consistent. This is a good indication that repeatability within each run order is consistent. Variability plots are particularly useful in determining different source of variations affecting the DOE. They also are useful in determining qualitative results for the DOE. Results for the electroform nickel stencil were very similar to those of the laser-cut stainless steel type.

Print DOE analysis. The stainless steel laser-cut and electroform stencil displayed similar behavior. Pad finish was shown to have the strongest effect on paste transfer efficiency. Next to pad finish, interaction between pad finish and stencil thickness appears to be significant. Stencil thickness is not the factor for QFP160 and TSOP32 as it is for 0402, 0201 and 01005. For miniature components, the thinner stencil appears to have better transfer efficiency than does the thicker stencil, due to a higher area ratio. As expected, absolute paste volume as the response shows stencil thickness has stronger effect. A thicker stencil delivers a higher volume of paste regardless of component type. For both stencil technologies, SPI and visual inspection showed no significant bridging for the components reported here.

Print DOE summary. It can be summarized from the above results, in regard to stencil thickness, that the thinner stencil (0.003˝) provided better transfer efficiency, while the thicker stencil (0.004˝) delivered a higher volume of paste. This is significant for miniature components, because a 0.003˝ stencil can provide adequate volume of paste with better transfer efficiency. Larger volumes of paste may not be desirable due to higher opportunity for assembly defects such as tombstoning and paste squeeze-out (bridging).

DOE analysis showed that regardless of the component type and stencil technologies, OSP finish provided higher transfer efficiency than ENIG. Further investigation is underway to understand the effect of pad finish on transfer efficiency.

In summary, the current study showed that all factors considered in this study (stencil thickness, stencil technologies, and pad finish) show significant effect on the printing process. In addition, complex interactions exist between these factors that need further study.

Board assembly study. Based on the results from the printing DOE, the board assembly study was designed as follows:

Variable factors:

• Stencil technology (laser cut stainless steel and electroform)
• Pad finish (OSP and ENIG)
• Reflow environment (nitrogen and air)

Fixed factors:

• Stencil thickness (0.003˝)
• Paste, Type 4 Alpha OM-350
• Optimum printing parameters (based on stencil technologies)
• Response factors:
• Visual inspection based on IPC-A-610D
• X-ray inspection
• Assembly defects (tombstoning, solderballing, missing components and bridging).

A fractional factorial DOE was conducted for this phase of the study to understand the effect of various land patterns and aperture shapes on component assembly. Three boards were printed per run order using the optimum print parameters with one squeegee stroke direction (rear to front) only. Components were placed on the boards and reflowed according to treatment combination. Reflowed boards were visually inspected to meet IPC-A-610D for solder paste characterization, and then x-ray inspection was performed. Table 4 shows the standard order design table.

Summarized analysis. Reflowed boards were inspected to ensure they met IPC-A-610D. Visual inspection clearly showed the overprinted pads (pads with more than a 100% pad-to-aperture ratio) did not cause bridging after reflow. In other words, the larger pads with excess paste showed good “pull back” characteristics. Visual and x-ray analysis showed that only passive components displayed defects, such as solderballing and tombstoning. Other packages such as QFP and TSOP showed no visual defects. All components showed voiding after reflow. Further investigation is necessary to fully understand the implication of voiding.

DOE analysis showed reflow atmosphere had the strongest effect on assembly defects. Board finish, which was a significant factor for paste transfer efficiency (from the print experiment), did not appear to be significant for board assembly.

Multiple DOEs were performed to understand the effect of various design and process factors on the overall assembly of boards with mixed-size components. Various statistical analyses were performed to determine the effect of stencil technologies, stencil thickness and pad finish on paste transfer efficiency. Results showed the 0.003˝ stencil provided better paste transfer for miniature components, while the larger components were not greatly affected by stencil thickness. In regard to the stencil technologies, laser-cut stainless steel and electroformed performed comparably.

Stronger than the stencil thickness effect was the pad finish. OSP pad finish showed higher paste transfer regardless of component size and stencil technologies. One of the explanations for this phenomenon could be the interaction between pad surface finish and paste chemistry. ANOVA analysis also showed a complex interaction exists between stencil and pad finish.

Based on the printing study, only a 0.003˝-thick stencil was included in the reflow DOE. Since the aperture design incorporated overprinting of larger components, a 0.003˝ stencil was believed better suited to study the effect of overprinting. The results suggest that nitrogen definitely improves the reflow characteristics of the solder paste with miniature components. Larger components had minimum-to-no effect in regard to the reflow environment. Unlike the printing results, pad finish had no significant effect on assembly yield. In regard to the effect of overprinting, results showed good pull back of the paste, causing no bridging. This is clearly encouraging. Visual inspection showed the fillet formation around the larger components appears adequate.

It is encouraging to see the 0.003˝ stencil with creative stencil design (overprinting the larger components) meets IPC-A-610D visual inspection criteria. This is a step in the right direction when dealing with mixed-size components. Additional work is underway to determine if the solder joints truly meet mechanical and long-term reliability requirements. 

Rita Mohanty, Ph.D., is director advanced development at Speedline Technologies (speedlinetech.com); rmohanty@speedlinetech.com.

Supply-chain roles are changing, with EMS firms expected to take a bigger chip-packaging role. 

As semiconductor packaging sees higher density interconnects and smaller scaling, it presents both a challenge and an opportunity for traditional electronics assembly providers. Previously, semiconductor wafers (produced by an OEM or a foundry) were shipped to an outsourced semiconductor assembly and test (OSAT) provider, where they were diced and packaged. Then the packaged devices were sent to an EMS facility to be soldered on a PCB or other substrate that would eventually become part of a finished system. Under this supply-chain flow, the tasks of the foundry, OSAT provider and EMS facility were completely separate, with each step in the semiconductor supply chain delivering the next level of assembly service from wafer to finished product. However, advances in semiconductor design technology, along with increased market pressure for higher density devices, yield improvements and cost reductions at all levels of the supply chain, have led the industry to rethink these traditional roles.

With conventional scaling of semiconductor line widths reaching its practical and economic limits, many chip designers have embraced some form of 3-D IC integration to achieve goals of higher-density devices. These new 3-D ICs carry implications for semiconductor packaging houses, as well as traditional EMS companies, providing an opportunity to expand their services.

3-D IC basics. To determine how 3-D IC technology would impact the various steps in the semiconductor supply chain, it is necessary to examine the different methods used to implement 3-D IC integration, and how they would impact current packaging and assembly processes.
Most 3-D IC designs begin with wafers developed using established high-volume processes to take advantage of foundries’ economies-of-scale. Many designs incorporate embedded metal through-silicon vias (TSVs), which form the interconnection between chip layers once the processed wafers are thinned to expose them, and then they are bonded to form the 3-D stack. If the 3-D integration is designed primarily to provide additional density, then the ICs being bonded can be of similar composition.

However, different semiconductor materials can be used to add functionality to a base IC layer, such as RF or analog functions that complement the overall system performance. Because different semiconductor materials require different – and often mutually exclusive – processing steps, some form of 3-D integration is the only method to produce such a hybrid chip without resorting to external packaging, which adds cost, complexity and bulk to the overall device.

The wafers (or die) used for 3-D IC integration are bonded using one of several methods: adhesives, heat and pressure, or direct oxide bonding (Figure 1). Each of these bonding technologies has specific limitations that can affect the overall yield, cost and interconnect density of the finished devices. Thus, the bonding technology has a direct impact on the ability of a semiconductor packaging and assembly provider to deliver 3-D IC integration services.

Adhesives. Adhesives are a common method for bonding semiconductor die or wafers. However, most adhesive materials cannot survive significant downstream wafer processes that require prolonged periods of elevated temperatures or pressures, so the resulting bond between the wafers does not exhibit the high level of mechanical robustness required for many portable electronic devices. Because of these process limitations, IC stacking is often limited to two layers. In addition, adhesive technology does not typically provide for interconnect, thus limiting the scalability of adhesive-based bonding schemes.

Copper-thermal compression. Another common method for ensuring a strong mechanical and electrical bond between wafers is metal-to-metal bonding, typically with copper as the bonding metal. In this process, wafers are aligned and then subjected to high (350° to 400°C) temperatures, while undergoing high pressure in multiple specialized chambers. The downsides are the high temperature has a negative impact on the CMOS; and the pressure needed affects the alignment accuracy and yields, and therefore, the scalability to smaller and smaller pitches is limited. Also, the time required in the specialized (read: expensive) processing chambers (up to 2 hrs. per wafer) dramatically impacts throughput (and hence, processing and tool ownership costs).

Direct oxide bonding. With direct oxide bonding, wafers to be joined are processed with embedded TSVs or tungsten plugs, which are exposed through wafer thinning. A layer of silicon oxide, combined with a bonding metal (such as nickel), enables the wafers to form a covalent bond at room temperature strong enough to hold the wafers together during downstream processing, forming a robust and reliable metal-to-metal interconnect bond. This technology can be used to build multiple layers of ICs with alignment tolerances of less than 1 µm, as tools for this purpose evolve, thereby providing advanced scalability.

The primary advantages of direct oxide bonding for semiconductor packaging and assembly providers are that it can be accomplished with minimal capital equipment expense (standard wafer pick-and-place and alignment tools, batch wafer heating processes); that it provides for high-yield, high throughput processing of multiple IC layers with high-density interconnections, and that it delivers the lowest overall costs for integrating 3-D ICs.
There are several specific processes for direct oxide bonding and chip interconnection, some patented.

We expect the role of semiconductor packaging and assembly firms to expand to include some form of 3-D IC integration. Those companies able to take advantage of the latest wafer and die bonding technology will become the suppliers of choice for leading manufacturers of portable electronic devices. 

Chris Sanders is director of business development at Ziptronix (ziptronix.com); csanders@ziptronix.com.

With a new building and equipment set, Leda is preparing to take off.

When Boeing (boeing.com) needs prototype assemblies, it jets on down to Leda Corp. (ledacorp.net), an aerospace design and PCB assembly firm located in the middle of Surf City USA.

There, in a cluster of innocuous white buildings in Huntington Beach, CA (Surf City is the town’s registered name), Leda operates a batch assembly line in a small footprint. But that’s all about to change.

President Joseph Tung and family – vice president (and son) David, and wife, Dorothy – own and operate Leda, a nearly 25-year-old firm that has been expanding steadily, if not rapidly, since it moved to this site in 2004.

The Tungs bought a second building on the campus in 2005 and a third nearby in 2006. And as construction workers diligently laid concrete and workers pieced together new equipment, Joseph Tung’s vision for the site would be realized in a matter of weeks.

Inside the 6,000 sq. ft. Building 2, an empty space in the floor marked where a new line would soon run. When a Circuits Assembly reporter visited the company in June, the new building was about 80% complete, and equipment was to be installed later that month. The staff numbers about 25, and once the site is finished the company plans to hire two or three more.

For Leda – the name comes from the first two letters of Joseph’s daughter, Leslie, and son David – it marks the culmination of a process four years in the making.

As David Tung explains, Leda is a small-volume, high-mix shop. “We do a lot of specialty jobs, but don’t do a lot of production.” Yet about five years ago, the company recognized it lacked capacity. The need became more pressing about two years ago, when the company missed out on an opportunity. The reason, David Tung believes, “is because we didn’t have a showcase facility with high-precision capital equipment.”

Steadfast in the aerospace/defense sector, the firm works with the prime aerospace companies, and is a preferred supplier to Boeing. “With a black box or flight instruments, you need three things: PCBs, cabling/routing, and enclosures/switches,” says Joseph Tung. That suits Leda, which provides all three. But it needed more capacity and a greater skill set. “You can’t use old technology because the components are too small to work with by hand,” he adds.

That should change with the addition of a new SMT line, which includes an Ersa printer, a Europlacer iineo pick-and-place machine, Ersa Hotflow convection oven, Mirtec AOI, and Nutek loaders and unloaders. As David Tung notes, “Everything is inline; we literally don’t have to touch a board.”

In keeping with aerospace sector’s demand for reliability and traceability, Leda’s new screen printer has built-in AOI, with a line-scan camera that will perform 100% PCB inspection. The company has opted for X-Tek x-ray and will continue to use existing equipment for board cleaning.

“This opens up their ability to bid on business, things they couldn’t bid on before with Boeing,” observes John Perrotta, vice president of Europlacer North America (europlacer.com), upon whom the Tungs relied for equipment and process consulting.

In evaluating choices for its new line, Leda opted for flexibility to meet the company’s need to change lines quickly and often. “We took a pretty close look at each element of the line we were proposing,” Perrotta says. “They opted for something unique in every case.”

“In this industry [aerospace/defense], capacity is really not an issue, because how many satellites can you build?” says David Tung. “Maybe 10 in the next 10 years. More often it’s just the quality of your product, high accuracy and the ease of changeover.” Leda plans for two to three changeovers a day, but the new line has capacity for 10.

“They don’t want to hire an army of people to support the line. There’s a reason they bought a fully automated line,” said Perrotta.

On the three-building campus, Leda plans to separate the product builds. Hardware will remain in the original building, while PCB manufacturing will be conducted in the second, and flight cables and fiber optics in the third. A unique element of the new layout is revealed by a long trench in the ground: All cables and piping will be routed under the machines in the floor of the facility.

The product mix for the new line will be 80% mixed technology. Components are kitted. Placement feeders are loaded with the next run’s parts and stored near the point-of-use.

Six months from now, when Leda fine-tunes its processes, its suppliers’ support will be more visible, but the company lauds its past support from equipment manufacturers, which the family sees as a key to its success.

Outside the factory, Dorothy Tung noted Huntington Beach is good for business because of the “influx of people and exposure of the company.” Still, the town presents its challenges. The firm currently is addressing the rejection of the oven’s transformer. “It’s either a city or Southern California Edison thing,” said David Tung. Leda needs to purchase a new transformer or build an explosion-proof enclosure around the existing one. Workers onsite said if this were any other city, the transformer would have been approved.

The company has been fortunate to be focused on the defense and aerospace sector, which has been less hard-hit during the recession. Founder Joseph Tung has long had ties to the aerospace industry. The Hong Kong native has a degree in engineering from Southern Methodist University in Texas. He then worked as an engineer for Boeing for six years, and on the first moon rocket in the 1960s in Huntsville, AL. He also worked for Lockheed on the Poseidon submarine program, and owned a company in Taiwan for 10 years that made toys and closed-circuit TV cameras.

Originally a PCB assembler, Leda gained ground when Joseph Tung convinced a buyer that a board design was wrong and would eventually fail. He talked to the engineer, and they agreed to change the design. Tung performed the redesign and Leda was off and running.

When Leda moved to the current building from what Joseph Tung described as a “three-car garage,” business doubled. The Tungs expect it to double again with the new line.

“Money is in enhancement,” said Joseph Tung. “You must have new machines to make old technology better, or you’re 10 steps behind.” Its latest investments should keep Leda flying high. 

Chelsey Drysdale is senior editor at Circuits Assembly; cdrysdale@upmediagroup.com.

Progress toward complete data packages has been slow.

Within board fabrication and assembly, there are several areas where improvements in information management are needed. The link between design and manufacturing, part traceability, and PWB systems all have new needs that can be addressed by improved information management systems.

There has been little progress in the transfer and communication between CAD and CAM systems. The problems fall into two main categories: incomplete information and non-intelligent data. Even today, most jobs coming into a fabricator or assembler contain incorrect or incomplete information. This may be in the form of missing data, an incomplete package description, the wrong data, or other inconsistencies within the data file. This lack of information greatly impacts cycle time and increases the chance for error. Intelligent data would further aid the transfer of information. Intelligent data uses complex data structures that associate attributes and even behaviors as one. This type of data would flow more easily through the data systems and improve interoperability.

Working with CAM tool suppliers, the industry has developed a diverse set of tools to automatically input a wide variety of formats, including automatic interpretation of aperture slits and tools to put some intelligence back into the data. However, this development seems redundant, as the design system already contains this information. Instead, a way of transferring this intelligent data is critical to the industry’s success.

Education about, and standardization of, the type and structure of information required for a complete printed board design package is necessary to eliminate the data transfer problem. This also includes standardization of component information for printed board assembly. Such standards have been developed and continually upgraded for years; however, progress toward more intelligent data exchange has been minimal. Non-intelligent Gerber data¹ remains the most common data transfer format. This format is error-prone due to issues with entering and interpreting aperture lists. Unfortunately, the industry has tried to push the Gerber machine language beyond what it was originally intended to convey. Part of the problem is the competitive nature of tool providers and their unwillingness to cooperate on a standard format. As long as this situation exists, it may be difficult to achieve highly organized, intelligent data transfer shown in Figure 1.

NIST’s 2004 report, Economic Impact of Inadequate Infrastructure for Supply Chain Integration,² estimated the lack of integrated IT systems cost the electronics industry supply chain nearly $3.9 billion per year. As most board fabrication is outsourced, the problem has been exacerbated in recent years.
With the rapid changes in component packages, many new orders are, in reality, new assemblies and new board designs. Because a large portion of the design changes with every order, traceability and configuration management have become important issues.

CAD/CAM needs. CAM continues to mature despite the issues between CAD and CAM systems. Many CAM suppliers have focused on providing automatic input of the wide variety of data formats, adding intelligence into Gerber data received, analyzing the data for manufacturability and, most recently, semiautomatic and automatic data editing. This focus has been driven by board manufacturers’ increased demands for faster tooling cycle time and better quality. More intelligent data transfer will enhance manufacturability.

The case also has been made for integrating the many steps in the preproduction process. This would have the dual effect of streamlining the process and decreasing the product time-to-market. It also would improve the overall design quality by providing feedback during new product introduction. Early fabrication involvement, clear communication of requirements, and maintaining the original design intent all would be byproducts of this integration. This process also would facilitate the engineering of new designs and reduce the number of times the design would have to be reengineered.

The 2009 iNEMI Roadmap³ identifies several PWB fabrication needs, including:

• More communication from CAD systems to CAM systems for fabrication (early manufacturing involvement, documentation, procedures, etc.).
• More intelligent, bidirectional, data transfer standards from CAD to CAM, containing information on physical boards (photoplot, legend stencil, solder mask, drill, materials, etc.), electrical (netlist, impedance, component designators, etc.), and component descriptions.
• A common data format to support data transfer between CAD and PWB CAM systems.

Traceability and issue resolution. Within a company’s factory network, an immediate understanding of a single product’s location is highly desirable to provide the most efficient and effective response possible to changing product demands. By creating a closed-loop system, information from the factory floor can be used as feedback, not only for the process control systems, but also for the product information systems. Wafer-level tracking is now available in fabs, while lot-level tracking has been common since the 1990s. In assembly and testing facilities, an individual unit is now traceable as it traverses the production line. A unit can be assigned a unique identifier that can be tracked through the production cycle. This makes product management at the lot and unit level feasible and beneficial. When coupled with a precise understanding of equipment fungibility, utilization and availability, unit tracking becomes a major advantage to the companies in the supply chain and, ultimately, to the end-customer.

In situations in which excursionary materials are identified “after the fact” and containment and disposition become important, use of material tracking in concert with corporate databases allows a rapid understanding of the location of “at risk” material and enables rapid response (Figure 1). Further, using this information to understand manufacturing cycle times, precise product volumes and unit location in the assembly line allows better optimization of production to meet demand. It also opens possibilities for starting new product manufacturing with minimal impact to existing production.

Another aspect of product traceability is to improve adherence to environmental requirements (both regulatory and business requirements) and aid in the identification of counterfeit parts. The unique ID can associate the unit with specific information related to the unit, such as material content data and manufacturing energy usage. By tracking the unit through the supply chain, a stakeholder can gain confidence that the unit traveled through authorized sources and is an authentic part.

The desire to collect traceability data highlights the need for factory information systems capable of collecting data from floor equipment in real time. In the past, assembly lines could be run somewhat open loop because the need to monitor every action was not necessary to produce product. However, collecting genealogy data for every product requires near-continuous communication between the machines assembling the product and the information management systems that pass those data through the supply chain. As a result, manufacturers are investigating methods for establishing communication between their applications and machines. Further infrastructure development to support the required traceability is needed.

Assembly information management. During the mid ’80s to mid ’90s, significant changes took place as the industry moved from through-hole to surface-mount technology. Over the past 10 years, innovation of assembly techniques has been relatively stagnant, as products commoditized and margins reduced. Manufacturers are reluctant to invest in holistic strategies for factory information systems. Although a long-term information management strategy will most likely save money, companies are investing in short-term solutions that may be suboptimal in the long term, but are perceived to have better cost-benefit ratios in the near term.

Large boards are usually assembled one at a time; however, smaller boards typically are laid out in a smaller panel (subpanel) in an array format. This array optimizes the assembly process. To obtain multiple panel images usually involves modifying the data machine language Gerber files or other drawing files for the fabricator. Two industry formats can improve this situation. One standard is hierarchal, looking through all the layers of the electronic assembly (IPC-2511⁴); the other is layered similar to Gerber machine data, however, with intelligent descriptions (IPC-2581⁵ and AP210⁶). Both formats are able to describe the board to panel or pallet relationship.

Unfortunately, this information usually is not provided to the board manufacturer. Historically, engineering and purchasing departments have not been inclined to work with the supplier to obtain the highest added value. Customers typically feel the challenge of making panels cost-effective rests solely with the supplier. This is a fallacy that needs to be corrected to establish some form of “cost of ownership” style of service for the end-user and supplier. In some instances, a specification is developed to capture the panelization strategy for board fabrication, as well as the assembly panel array (pallet). The details of the specification, however, must be flexible enough to allow choices by the fabricator in terms of optimum panel sizes. This is a cost driver and it impacts yield calculations and resulting profits.

In addition, in-depth discussions must take place with the assembly resources, as they are the users of the panel and have to deal with the breakaway methodology, testing demands and optimum throughput size for their process. Whether scoring, routing (leaving tabs) or a combination, the depanelization strategy should always be reviewed with the supplier during fabrication and assembly. Figure 2 shows the movement from fabricator to assembler, plus the data and naming descriptions that accompany those transfers.

Existing standard information models cover the board, assembly, the fabrication panel, the assembly array panel, all fixtures (electrical bare board test, in-circuit test, assembly, etc.), and the electrical test vectors. The solder stencil can be extracted from files based on these models. Presently, however, it is generated from the machine language Gerber data. Stencil openings are then modified to provide the optimum amount of solder paste to maximize the solder joint quality, and component placement data must be loaded separately into the placement equipment. Because of different design software packages with no common output format, there is no direct input of data into the placement equipment. There is also diversity in the way the designs are described, such as differences in the way the 0,0 reference point is defined and communicated to the assembler, no orientation or physical size of the component provided, differences in the parts nomenclature, and different types of bill of materials.

Printed board assembly needs include:

• The ability to transfer data from the design system to the assembly equipment via some format with more intelligence that will support the development of test data, automatic generation of component placement data, and data for failure analysis of defects.
• Consistent naming conventions for all component types (common component libraries), such as those defining component type, length, width, height, centroid data, etc.
• Sophisticated design rule checking in the CAM environment.
• Design tools that implement manufacturing rules, similar to those used in the semiconductor industry where process rules drive design methodologies.
• New test strategies, utilizing intelligent data from the CAD system.
• A common data format to support data transfer between CAD and assembly CAM systems.

Conclusion

Improving standards for design and manufacturing data, and implementing these standards consistently in information management systems and manufacturing equipment, will enable higher productivity and low costs.

The Information Management Systems chapter of the 2009 iNEMI Roadmap provides a more complete summarization of the gaps/issues faced (inemi.org/cms/
roadmapping/2009_roadmap.html). 

References

1. Barco Graphics, “Gerber RS-274X Format User’s Guide,” 1998.
2. NIST, “Planning Report 04-2, Economic Impact of Inadequate Infrastructure
   for Supply Chain Integration,” June 2004, nist.gov/director/prog-ofc/report04-2.pdf.
3. iNEMI, 2009 iNEMI Roadmap, April 2009.
4. IPC-2511B, “Generic Requirements for Implementation of Product Manufacturing Description Data and Transfer XML Schema Methodology,” January 2002.
5. IPC-2581, “Generic Requirements for Printed Board Assembly Products Manufacturing Description Data and Transfer Methodology,” May 2007.
6. AP 210, “Standard for Electronic Assembly Interconnect and Packaging Design,” (ISO 10303), April 1999.

Eric Simmon is an electrical engineer in the Electronics and Electrical Engineering Laboratory of NIST’s Electronic Information Group, Semiconductor Division; eric.simmon@nist.gov. He chaired the Information Management Systems chapter of the 2009 iNEMI Roadmap.