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It was Apex vs. the economy, and the economy won.

In 2009’s first test of how the electronics manufacturing industry is holding up, the crowds mostly stayed home from the major North American trade show of the year. Travel bans at several major OEMs clearly dampened Apex turnout in April – down 34% year-over-year. Sensing the pending void (and disgruntled over the inflated costs of the show), exhibitors scaled back on equipment and booth sizes and, in a few cases, pulled out altogether. Perhaps Rehm COO Marc Daldrup summed it best, calling it "a real survival year."

One survivor was the technical conference, which held its own with last year. Overall numbers were solid, even though several traditional classes were canceled due to lack of registrants. The standards-writing task groups were busy as well, as the organization’s primary documents, including J-STD-001 and IPC-A-610, are undergoing revision.
According to members of the task groups authoring the documents, much of the review of the two popular documents centers on eliminating the conflicts in the qualification criteria. The J-STD-001E revision appears on track for completion well ahead of IPC-A-610E, but publication of the former will be held to coincide with the latter, a task group member told Circuits Assembly. “What is good,” the member said, is that the respective task groups are giving the documents “a very thorough scrub” to be sure there are no conflicting criteria. The goal is to have them done by Apex next year, says IPC vice president of standards and technology Dave Torp.

Two other joint standards, J-STD-004 and J-STD-005, covering fluxes and pastes, respectively, are undergoing updates to incorporate low halogen versions (generally defined as less than 900 ppm of chlorine or bromine, and a total of less than 1500 ppm of both). Henkel Electronics Global Marketing Manager Doug Dixon said the solder materials company has seen “significant activity” on halogen-free materials, while noting a cost-savings in refrigeration and the reworkability of such products.

Some of the test methods need to be revised for finer pitch components, Torp told Circuits Assembly. For example, the silver chromate paper test (IPC-TM-650 method no. 2.3.33) doesn’t detect halides at certain levels and is prone to false positives from the presence of certain chemicals. Some of the lessons learned from the Pb-free process need to be incorporated as well, Torp said.

One proposed document generated a small amount of controversy. According to several technical committee members, IPC is pushing for a box build standard. The response, the members told Circuits Assembly, ranged from disbelief to amusement. (“It would be a one-sentence standard: ‘Build per manufacturer’s specifications,’ ” joked one member). Others pointed to extensive existing documentation in the plastics and sheet metal arenas and claimed any efforts by the electronics industry would be largely redundant. “It’s going to be another big standard,” Torp acknowledged. “It will take years to develop. But there is a demand for it.”

Continued attempts to attract designers under the IPC umbrella were a complete bust.

‘An Inspection Breakthrough’

The show floor had its moments of noise and congestion, but they were few (Figure 1). (Official attendance numbers were not available in time for publication.) Many exhibitors had equipment, although the number of machines in toto was certainly lower than in past years, and almost every machine was in dry run mode – if switched on at all.

Fig. 1

The most impressive advancement on the technology side was a product that, as of this writing, officially hasn’t even been introduced. Koh Young (kohyoung.com), known for its SPI equipment, has leveraged that eight-way light projection platform for a new 3-D AOI that, in the words of a couple EMS engineers who saw demonstrations, “could be a game-changer.” The as-yet unnamed inline machine, which Circuits Assembly saw in action, offers topside 3-D inspection and bottom-side 2-D inspection. It looks for six types of failure: overhang, solder fillet, coplanarity, component dimensioning, markings and bridging. It uses IPC-A-610 as a measurement benchmark (the guidelines are incorporated, with supporting images, in the software), and compares images taken (a 4-MP camera is onboard) to the CAD data, thus eliminating use of a golden board – not to mention the operator’s visual comparisons. The software is simple, containing no menus or sliders, and its library contains component shapes and dimensions. The 3-D imaging was a treat: A bridging defect showed the distinct ripple of the solder; a coplanarity defect could be measured in quantifiable terms (Koh Young claims accuracy of 10 to 30 µm). If it works in the field, this machine will turn more than a few heads.

The other distinct advancement we saw was in soldering. Heller (hellerindustries.com) showed its new Mark 3.5 Series reflow oven, whose 10" zones caught some eyes. And Rehm (rehm-group.com) had its Dual Lane Vision X convection reflow oven, which comes with two conveyor lanes that can be operated asynchronously at different speeds, enabling simultaneous lead-rich and Pb-free soldering (Figure 2).

Fig. 2

Zestron (zestron.com) introduced a cleaning chemistry called Vigon N 500 that is novel for its pH-neutral formulation. Although cleaning remains fairly uncommon among most EMS companies, its penetration rate is ramping as concerns become more widespread over the residues left by Pb-free alloys. Kyzen (kyzen.com) and Aqueous Technologies (aqueoustech.com) are also said to be enjoying both increased interest and orders as a result.

Apex this year took on a distinctly regional feel. Attendees were visibly American, with precious few Europeans, Mexicans and Asians represented. While quick to cite the economy, many exhibitors expressed hope (or concern) that the lousy business environment isn’t masking a further regionalization of the major trade shows.

Apex is the first of the major electronics manufacturing trade shows this year. What can we expect going forward? Most observers Circuits Assembly spoke with felt Nepcon China, in Shanghai later this month, would be slower than in the past, and relatively devoid of US and European attendees. The consensus is that, assuming a economic upturn this fall, SMTAI would benefit from its timing (October) and location (San Diego), while the biennial Productronica – still the Mother of All Trade Shows – would be solid from an attendance standpoint even if the booths – often extravagant shows of “Can you top this?” – are restrained relative to previous years.

As for Apex next year, timing is going to be an issue. The show is scheduled for April 6-8. Easter Sunday is April 4. As one exhibitor noted, “I guess Christmas was taken.”

Service and Innovation Recognized in Uncertain Times

Anyone who says this year’s Apex trade show was empty did not attend the reception for the Service Excellence Awards and New Product Introduction awards. While the trade-show floor was sparser than usual, the event kicked off the week properly, with some 150 participants and guests converging to learn the results of Circuits Assembly’s much-anticipated programs.

In its 17th year, the SEAs for electronics manufacturing services providers and electronics assembly equipment, materials and software suppliers recognized the companies that received the highest customer service ratings, as judged by their own customers.

In the EMS category, overall winners were Mack Technologies (sales above $100 million), EIT Inc. (sales of $20 million to $100 million), and Krypton Solutions (sales under $20 million). Mack and Krypton were repeat sequential winners, while EIT earned its first SEA accolade.

EMS companies with the highest scores in each of five individual service categories also received awards. (Overall winners were excluded from winning individual categories.) In the small-company category, newcomer Sunburst EMS held the top spot in the areas of dependability/timely delivery, responsiveness, technology and value, while tying with second-time winner Screaming Circuits in the quality category.

In the medium-company category, Western Electronics took highest honors for dependability/timely delivery and value. Electronic Systems Inc. and Applied Technical Services won for quality, while MEC Companies excelled in responsiveness and tied with Applied Technical Services for technology.

In the large company category, EPIC Technologies swept all five individual categories.

Electronics assembly equipment award winners were Asymtek for dispensing; Assembléon for pick-and-place; BPM Microsystems for device programming equipment; DEK for screen printing; Kyzen for cleaning/processing materials; Mirtec for test and inspection, OK International for soldering equipment, EFD for materials, and BEST Inc. for rework/repair. Aegis Industrial Software received top honors yet again in the manufacturing/supply chain management software category.

A donation of $2,500 was made on the participants’ behalf to the Surface Mount Technology Association’s Charles Hutchins Educational Grant.

In its second year, Circuits Assembly’s 2009 New Product Introduction Award for electronics assembly equipment, materials and software suppliers recognized leading new products for electronics assembly during the past 12 months. An independent panel of practicing industry engineers selected the recipients.

The winners were ASYS for automation tools for the FIFO Buffer System FPS30B; Speedline in the category of cleaning equipment for the Electrovert Aquastorm 100; Kyzen for Aquanox A4241 in the cleaning materials category; Juki Corp. for component placement – high-speed and multi-function for the FX3 and JX100, respectively; BPM Microsystems in device programming for Flashstream -C; Asymtek for the DispenseJet DJ-100 in the dispensing equipment category; labeling went to Polyonics for Product Sentry; materials-flux went to Nihon Superior for its NS-F850; KIC took home the process control tools recognition for RPI, and VJ Electronix for 400ST in the rework/repair tools category.

Milara’s TD2929 Automatic Inline Printer and Assembléon’s Yamaha YGP tied for screen/stencil printing; Juki took home software-production and software-selective for Intelligent Shopfloor Solutions and its Flex Solder Series, respectively, while Henkel scored the title for soldering-materials for its Multicore LF700; Heller Industries was recognized for soldering-reflow for the Mark 3.5 Series, while soldering-other went to EVS International for EVS 7000 Solder Dross Recovery.

Finally, soldering-hand tools went to OK International for the Metcal MX-5000 Series, and test & inspection-AXI went to Dage Precision Industries for Dage XD7600NT100; Agilent was honored for test and inspection-ICT for Cover Extend; Mirtec’s MV-3L finished in the top spot for test and inspection-AOI, and underfills went to Henkel for Hysol UF3800.

In a rough market, these programs remind us industry firms are still providing customers with new technology and the assistance to support it, and these companies will guide us into the next phase of prosperity.

Look for photos of the awards reception on the Circuits Assembly website in the coming weeks, and find out about the 2010 programs toward the end of summer. – Chelsey Drysdale

Mike Buetow is editor in chief and Chelsey Drysdale is senior editor of Circuits Assembly; mbuetow@upmediagroup.com.

 Chinese

And do independent lab results support its use?

Increased interest in halogen-free assemblies is a result of Non-Government Organizations (NGOs) exerting pressure on electronics manufacturers to eliminate halogens. The NGOs’ primary focus is on resolving global environmental issues and concerns. As a result of an increase in the enormous e-waste dump sites around the world, NGOs are pushing consumer electronics manufacturers to ban halogen-containing material in order to produce so-called green products. Not only are these sites enormous, but the recycling methods are archaic and sometimes even illegal. This stockpiling and dumping has created growing political and environmental issues. To deal with this issue, the question of why halogens are a focal point must be addressed.

As a safety measure, halogens are added to organic materials as a fire retardant. The common halogens used only emit bromides under elevated temperatures, decomposing and releasing bromine to extinguish fires. These are toxic as well as corrosive when decomposing. However, they are benign at ambient temperatures. The jury is out on the replacement products for these brominated organics, with uncertainties about long-term health exposure and environmental impact.

Rather than replace halogens with potentially equally harmful substitutes, it would be more logical and effective to address this issue at the e-waste sites. If modern recycling processes were applied to these sites, this environmental problem could be minimized. Methods such as shredding followed by fluid bed separators could yield higher value returns for the recyclers and mitigate the impact of the halogens.

Nevertheless, electronics OEMs are feeling pressure from NGOs and are moving toward halogen-free electronics assemblies. That, in turn, trickles down to the suppliers of electronics assembly materials, board materials and components. The general trend is that every component subassembly on the board must be halogen-free. Other committees refer to these component subassemblies as substances, articles and/or preparations. Solder paste and flux products are included in these restrictions. Some electronics OEMs require solder pastes to be tested; some want the flux tested; yet others want combinations tested.

Solder paste that creates the electrical and mechanical connection on a circuit board now constitutes the article. The rules of sample preparation regarding dilution should apply, as they are consumed in one unit. So what is halogen-free? Many committees, consortia and organizations are working on this issue. Some organizations have published maximum limits as the determining factor. These can be 900 ppm of either bromine or chlorine and a combined total of 1500 ppm. Others have set 1000 ppm of either bromine or chlorine. There is an attempt to have a defined limit on halogen content (Table 1).

Table 1

How does one determine if a solder paste is halogen-free? The most popular test method is known as “oxygen bomb,” which is a combustion test immediately followed by ion chromatography. This is an environmental test procedure and may be performed in a variety of methods. The most popular seems to be BS EN 14582:2007; although other test methods are available, including EPA SW-846 5050/9056 or JPCA ES-01-2003.

Table 2

We conducted round robin testing to determine repeatability of halogen-free testing results to EN14582:2007. We manufactured a batch of solder paste medium (“NC-A”) intentionally doped with 13,000 ppm bromine, as well as a completely halogen-free version (“NC-B”). All samples were chlorine- and fluorine-free. Solder paste was manufactured with these two mediums; the medium itself for NC-A was also sent for testing. The solder paste was composed of 89% metal, with the balance being the medium. We prepared these three sample types and sent them to six independent testing laboratories around the world. Results are shown in Table 2 and Figure 1.
Based on testing performed by six different laboratories, all of which used the same method, it is readily apparent that the precision of this testing method is poor.

Fig. 1

An interaction between the metal alloy and flux medium in a solder paste was also observed. Figure 2 shows a notable difference between the NC-A flux medium made intentionally with 13,000 ppm bromide added and the NC-A SAC 305 solder paste of the same medium. Because solder paste is 11% by weight medium and 89% by volume metal (in this case), one might expect a 11% drop in reported bromide or 1430 ppm, which is not the case. Additionally, there is no consistency in the net difference reported between laboratories, further suggesting lack of repeatability in the test method. This also points out that testing of the medium alone for compliance is not recommended because the bromide levels are reduced or consumed when mixed with the alloy in the solder paste.
When these mediums are tested to J-STD 004, no halides are found. However, the current IPC test does not detect halogens. To fail the IPC test, the halogen has to be ionic and soluble in water/alcohol. Based on the test results following this IPC standard, these pastes and mediums are halogen-free.

Fig. 2

Further testing would need to be completed to determine if a reflowed residue contains halogens, as all of the above were run on unreflowed paste. This further complicates the current test methods because of the extra step to extract the reflowed residue and the potential of compromising sample integrating. If further reduction or consumption of the halogen content takes place, then soldering fluxes and paste would have virtually no impact on a board, component or subassembly relating to halogen content of the final product.

Table 3

SIR results for the halogen-free versus the halogen-containing products in this study indicate the halogen-containing product has slightly better SIR values than the halogen-free equivalent. This is due to the relatively low amount of organic activators required to interact with the halogen to get acceptable soldering results, whereas the halogen-free products require a much higher concentration of organic activators that have a slightly negative effect on SIR values. Table 3 and Figure 3 compare the SIR values of the two pastes used in this study.

Fig. 3

The electronics assembly industry is being pushed in the direction of halogen-free materials. Already, many manufacturers around the world are pushing suppliers to provide materials to meet the criteria of this latest industry buzzword. However, many questions concerning this issue remain: If we do want halogen-free, what are the gauge R&Rs of the test procedures? How critical is 1500 ppm versus 900 ppm? Is this a test that represents the real impact of the halogenated fire retardants? Should the halogen content only be tested on the final assembly? Brominated fire-retardants were introduced to eliminate the more toxic antimony oxide previously used. What are the impact and the danger of the replacements? How pertinent is this to electronics assembly when the real issue is illegal dumping of e-waste? The results of the testing regarding this topic create more questions than answers. Until these questions are answered, the attempt of OEMs and their suppliers to meet the requirements of NGOs to provide halogen-free products is confusing, unduly expensive, disadvantageous, and potentially more harmful than supplying halogen-containing materials.

Karl Seelig is vice president of technology and Michael Burgess is strategic account manager at AIM (aimsolder.com); kseelig@aimsolder.com.

The Defects DatabaseVibration and strain from Pb-free solder can crack traces near PBGAs.

This month we feature one recent issue on broken circuit traces on an area array design. A large plastic BGA was found with open circuit connections on the corners of a package. The assembly reportedly failed in the field in a telecommunications application produced in medium volume. Nondestructive x-ray examination confirmed broken traces leading to the corner termination pads. The PBGA was mounted on a standard 0.63" epoxy-glass substrate and soldered with Pb-free solder.

Fig. 1 and 2

The probable cause may be expansion and contraction of the package and board during local high-temperature operation. If the pad surface had separated from the board (a condition known as pad cratering) because of mechanical shock or high Tg laminate use, the failure could occur more quickly.

An alternate possibility may be the impact of vibration on the joint interfaces: Pb-free joints are stronger and more rigid, so strain may be transferred to the traces. Closer examination of the broken trace, the quality of the original connection, trace/pad and analysis of the operating environment is required. This type of failure has been seen on flexible circuits due to the strain of flexing.

These are typical defects shown in the National Physical Laboratory’s interactive assembly and soldering defects database. The database (defectsdatabase.npl.co.uk), available to all Circuits Assembly readers, allows engineers to search and view countless defects and solutions, or to submit defects online.

Dr. Davide Di Maio is with the National Physical Laboratory Industry and Innovation division (npl.co.uk); defectsdatabase@npl.co.uk.

Getting LeanNothing beats hands-on training and built-in flexibility.

Much has been written on implementation of Lean manufacturing philosophies on the factory floor. However, the most efficient Lean systems grow out of Lean cultures, where everyone contributes to continuous improvement. EPIC’s training program is a core building block of its Lean philosophy. It focuses on three primary areas:

  • Lean principles.
  • Job skills and operator certification.
  • Cross-functional training tied to EPIC’s Synchronous Flow Manufacturing (SFM) process.

A core principle of the SFM program is flexibility. Production systems and processes are designed to maximize throughput. At an equipment level, this has translated to a common equipment strategy that utilizes machines capable of broader process windows and minimized changeover times. However, the company’s philosophy also considers the human factor. EMS providers have a challenge in implementing Lean manufacturing because, unlike an OEM, they lack complete control over production demand. EPIC addresses this by providing information systems and a robust cross-training program that allows production operators to shift between work areas as demand dictates. The result: a highly flexible, efficient production floor where resources are deployed as demand dictates.
The Quality team is integrated into the organization, working closely with direct and indirect employees and the processes that make up the quality management system. This is the primary reason the training function is overseen by the Quality department and fully supported by senior management.

All employees are trained in Lean methodology and company objectives, and undergo a core training program. The core training program was developed to lay the foundation for Lean principles and a culture driven by continual improvement. Training is given to all employees and refresher courses conducted annually. Elements of this core training include safety, IPC-A-610 overview, and Kanban.

Although Lean concepts are universal, EPIC’s manufacturing environment is unique and training needs to be tailored to accommodate its approach. One example would be the Kanban training program. In addition to teaching students basic Kanban principles, students are tested on sample racks seeded with problem issues that they must effectively troubleshoot. Sitting in a classroom receiving mass training material is not nearly as effective as the “hands-on” approach. This is one of the drivers of improvements within the training program and the ongoing evaluation process for all employees.

To meet customer demands and remain flexible, it is critical for the Lean company to have strong relationships with temporary staffing agencies. To improve the screening process for potential new hires, EPIC teamed with a local temporary staffing firm to initiate a custom training/screening program. The company and staffing firm co-developed the program with the goal of enhancing the explanation of its electronics manufacturing culture to potential hires and screening these applicants through a series of tests. EPIC-defined “criteria” assist the staffing agency toward only bringing in qualified applicants. This initiative has kept the temporary turnover rate consistently below industry average levels. Industry-standard resources are also used for a portion of the core and job skill training. For example, IPC-generated resources include:

  • Introduction to IPC-A-610D using an internal IPC-certified instructor.
  • ESD training.
  • IPC-A-600 training for bare board inspection using an internal IPC-certified instructor.
  • IPC-7711/-7721 training on rework and repair using an internal IPC-certified instructor.
  • Six Sigma training is also being added to Lean curriculum. Six Sigma Black Belts were hired and are now training
  • Green Belts at multiple sites.

Training translated to flexibility. Once the core training is completed, there are specific training paths for indirect and direct personnel. Indirect personnel training includes placing employees directly on the production floor before learning the specific tasks defined in their job description. This time spent rotating through production areas ensures familiarity with critical electronics manufacturing processes.

Job descriptions are integral in driving workforce flexibility. Each indirect job description includes a corresponding training checklist to ensure each person performing that job has been trained in all competencies required for the position. This flexibility is built into the job descriptions/training checklists to focus not only on that specific job, but also to incorporate cross training. This gives the employees a much broader scope of how things work and enables them to assist other disciplines within the company. Each job description or training checklist includes:

  • Job summary.
  • Essential duties and responsibilities.
  • Competency requirements.
  • Education and/or experience requirements/qualifications.
  • Core training requirements.
  • Departmental training.
  • On-the-job training on the processes.
  • Procedural review.
Fig. 1

Operator certification for direct employees ensures that operators are qualified to perform assigned duties. To facilitate a flexible direct workforce, a core training matrix is used to identify all competencies of all the people on the floor. There is an assignment board with all the major processes with cards showing staff color-coded by shift. Team leaders on all shifts assign work areas, and employees check the board at the beginning of a shift and after each break (Figure 1). The result is a Lean production team schedule based on production demand and worker competency. It is important to note that team members aren’t simply viewed as additional resources of production. Instead, they are considered to be integral elements in the company’s focus on continuous improvement, and the expertise gained in performing multiple tasks is highly regarded. Cross-functional team members can make improvement suggestions anywhere in the company. Some of the best ideas for product, process and safety continuous improvement initiatives come from the employees working directly in the processes every day.

Tony Bellitto is quality manager-US Operations, and Patience Day is Norwalk training coordinator at EPIC Technologies (epictech.com); tony.bellitto@epictech.com.

Reflow SolderingForcing science on the long-held “art” of profiling.

Art is the use of skill and imagination in the production of things of beauty. Is a reflow profile art? It could be, provided the result of the profile is a robust, repeatable reflow process. However, learning the art of reflow profiling is a long, imaginative road. Once mastered, it still requires significant time and effort.

Science is knowledge covering general truths or the operation of general laws, particularly as obtained and tested through scientific methods. Can science be applied to reflow profiles? Absolutely. Construction of general laws related to forced convection reflow oven characteristics permits fast, robust development of an in-specification profile, important to ensure good solder joint formation, high yield rates and assembly reliability. An optimal profile takes into account the specifications of the solder paste, the various components and laminate, while also taking into consideration the oven capabilities (e.g., a reflow oven with more heating zones has more flexibility than shorter ovens when it comes to meeting specs).

A reflow profile breaks down as follows:

  • Ramp-up heating rate is the positive change of temperature per unit time. Typical specifications list a maximum of 3°C/sec. Defects associated with exceeding this rate are component damage, poor solder paste slump, or adverse effects on flux evaporation and activation characteristics.
  • Thermal soak is the time and temperature required to level temperature across the board before reflow. However, when temperature equilibrium is easily achieved due to simple boards and good oven heat transfer, this soak interval can be eliminated. (This is known as a linear profile.) Thermal soak represents the flux activation and subsequent cleaning of oxides from all surfaces.
  • Time above liquidus (TAL) is a defined range of time that the PCB is held at a temperature above the solder melting point. Defects associated with insufficient TAL are poor wetting and incomplete joint collapse, while defects associated with excessive TAL are formation of thicker, brittle intermetallic layers; potential board or component failure due to exposure, and dewetting.
  • Peak temperature is the maximum temperature allowable for different components and solder paste. The combination of solder paste specifications, component moisture sensitivity level (MSL) and laminate requirements limit the maximum possible temperature. Defects associated with exceeding Peak Temperature are the popcorn effect observed in components, delamination, cracking, and lifting observed in the laminate.
  • Cooling rate is the negative change of temperature per unit time. Typical component and solder specifications limit the negative value to greater than -6°C/sec. Defects associated with exceeding the limit are based on the CTE mismatch of the system; i.e., excessive cooling induces stress at the interfaces of the component body, solder and laminate.
  • Total heating time is the time available to optimize the aforementioned factors and is typically specified by the solder paste manufacturer.

Envision this scenario: A new employee, without prior profiling experience, is tasked with profiling a PCB. You tell them which paste to use and then point to an oven. The complexity of profiling process is underscored by the confusion on the rookie’s face followed by the cascade of questions: How fast should the conveyor go? What temperatures do the heaters get set to, and how do you know that? The answers are based on board size, an intuitive understanding of heat transfer, oven behavior and process tradeoffs. You might have profiled a similar board in the past and can reference that experience to come up with a starting point for heater set points and conveyor speed. However, sans that inventory of profiling experience, it might take a new employee several iterations to develop the desired process.

The solution is to develop a database of profiles that capture the process engineer’s experience combined with profiling expertise. The database would

  • Shorten the process development learning curve.
  • Be organizationally available to everyone to use.
  • Remain within the organization, not individual-dependent.
  • Reduce the time to develop profiles by minimizing the conventional pitfalls of the “first guess” at process set points.
  • Provide a consistent approach and results.
  • Not require the process engineer to start developing profiles.

We addressed this by developing a product to provide an in-specification or near specification reflow profile with minimal profiling (or none) needed. This was achieved by populating databases with various types of profiles, including those based on SnPb or Pb-free, as well as linear or ramp soak spike reflow types. A proprietary test vehicle was designed to simulate PCB board types of varying complexity, from simple two-layer to complex 16-layer PCBs, for the purpose of populating the databases. This test vehicle, along with commercial profiling software, was employed to systematically optimize profiles for a variety of pastes, profile shapes and board types.

The criterion employed to evaluate the accuracy of both the predicted and validated profile was the Process Window Index (PWI). PWI takes into account measures of the aforementioned reflow profile attributes and provides a single number to indicate compliance with the specification or to what degree. A PWI value equal to or less than 100 is indicative of a profile that meets all reflow process specifications. A PWI value between 101 and 200 is indicative that at least one reflow process parameter is slightly out of spec. Table 1 lists examples of PWIs between 101 to 200 and the corresponding “out of specification” reflow parameter.

 Table 1

An evaluation was undertaken to gauge the accuracy and precision of predicted reflow profiles. In total, 56 unique profiles were predicted and ranked based on the precision of the defined parameter specifications. These unique profiles were characterized by the selective combination of 11 different process windows applied to seven different boards. Actual PCB dimensions ranged from 8.5" x 6" x 0.40" thick with a mass of 74 grams to 17" x 11.2" x 0.125" thick with a mass of 1,260 grams. (The latter was validated with instrumented BGA balls to make the assessment more relevant and challenging.)

The results show that 55% of the validated profiles achieved a PWI less than 100. In these cases, the profile satisfied all process criteria. The second group of data contained 33% of profiles characterized with PWIs between 101 and 200. Figure 1 shows results of the PWI for the 56 validation runs. The box contains 75% of the data points per PCB type; the horizontal line represents the median, and the cross hair represents the mean.

Fig. 1

While no trend is readily apparent, second-level testing using a third-party system validated the following conclusion: 88% of the predicted profiles required either no further optimization or one iteration to develop of a robust reflow process.

The advantages of a data-driven reflow profile prediction tool are significant to any electronics manufacturing organization. This tool and the data satisfy the six objectives, and illustrate how science can be applied to what was traditionally held by the electronics industry as art.

Jon Silin is process technician at Vitronics-Soltec; jsilin@vsww.com. Ursula Marquez de Tino is a process and research engineer at Vitronics Soltec, based in the Unovis SMT Lab (vitronics-soltec.com); umarquez@vsww.com.

Better ManufacturingReplacing actives with bare die reduces the footprint as much as sevenfold.

As electronics technology progresses, system miniaturization drives more function into smaller and lighter packages, increasing package density. The tighter line widths and spaces and smaller vias required by the increase in density are ideal for high wireability packaging solutions. In applications where all required functions cannot be implemented on a single chip, using system-in-package (SiP) best answers the miniaturization need without sacrificing performance.

Traditional system assemblies consist of a printed circuit board with numerous packaged modules, components and connectors for communicating outside and within the system. All these electronic devices and components communicate through the board, integrating a variety of functions. Redesigning these devices and component assemblies into a SiP significantly reduces the number of components necessary for the system to function. By replacing the packaged components with bare die, sweeping the passives off the board surface, migrating to fine-pitch connectors and incorporating high-density interconnects, the size, height and weight of the product can be significantly reduced.

SiP uses bare die to get a lot of function in a small space. Replacing active packages with bare die reduces the required footprint for that particular function as much as sevenfold, and significantly reduces pad size and pitch on the substrate necessary to accept the bare die bumps. These small, tightly spaced pads will typically require solder to be applied to the substrate before assembly to connect the flip-chip bumps on the bare die to the substrate. Using the correct amount of solder is critical: Enough solder must be applied to form a good joint, but too much solder will bridge the joints during soldering. However, this approach drives a very dense and advanced substrate design, fabrication and assembly. Analog, digital, and memory flip-chip devices are mounted on the SiP using advanced substrate methods.

On traditional assemblies, capacitors, resistors and inductors usually dominate the board surface. Embedding capacitance material into the structure of the substrate minimizes the requirement for a number of these components, but also increases fabrication complexity and material costs of the substrate. Applying thin-film resistor materials to copper foils or screening resistor materials enables the resistor technology to be embedded into the SiP substrate. These materials can then be trimmed to the required value using a laser.

To optimize functionality, the large connectors are replaced with fine-pitch connectors. Replacing large, bulky connectors with patterning interconnects that have fine-pitch edge mounted units greatly reduces substrate size. This technique also optimizes the functional area of the package where most of the critical system communication is required. A single 1 mm space connector can reduce the connector(s) footprint by 5X, but will result in higher wiring demands of the substrate to enable in-and-out wiring of the perimeter-mounted substrate.

The substrate must be able to support HDI, which is essential to minimizing size and weight and maximizing performance. An advanced SiP requires high wireability, not only in the x-and y-directions with small circuit lines and tight spacing, but also in the z-direction to accommodate communication between tightly spaced components on both the top and bottom of the substrate. To provide an order of magnitude, this means a substrate at least 25 µm circuitry traces, 50 µm diameter microvias, and 5 µm diameter plated through-holes. The increased interconnect density increases the number of components placed in a given area. HDI is the best method for evenly and effectively balancing the SiP design with component placements on both sides of the substrate.

To provide a smaller package with increased performance and usability, an effective SiP requires a combination of advanced substrate features and component miniaturizations, all of which interact to achieve the desired package function and performance requirements. Active devices and components must be removed from their traditionally large packages and assembled directly onto a substrate designed to accept direct chip attach. Embedded passive layers and components must replace the traditional surface mounted components to free critical substrate space, which in many cases will improve the electrical performance of the package. Communication off the substrate must be consolidated and minimized with new connector solutions, and the placement of all these devices and components will be critical to overall package size reduction and performance. These requirements drive dense component placement and demand dense routing requirements of the substrate. The substrates necessary for a SiP with bare die can be more costly, and the fabrication and design more complex, but the benefits of a smaller, lighter, and higher-performing product usually outweigh the development difficulties.

Ed.: We welcome Jeff Knight to our lineup of columnists. His column will run bimonthly.

Jeff Knight is vice president of business development at Endicott Interconnect Technologies (eitny.com), jeff.knight@eitny.com. 

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