Rigorous testing found local vapor phase clearly superior to alternative processes.

We report in this work the development of a rework method that uses local vapor phase technology to attach a large 14 x 120 receptacle connector. This large connector supports 6 Gb/s single-ended mode signaling at a contact density of approximately 28 contacts per cm2, and plugs a single processor node into one of eight mid-plane header connectors. Its approximate external dimensions are 28 x 5 x 4 cm. It supports 5,040 I/O and is surface mounted to a 4 to 5 mm thick printed circuit board. Figure 1 shows the connector at the edge of the PCB.

The connectors are made from individual wafers that are interference-fit into stainless steel organizers. The individual wafers possess signal contacts on one face and ground contacts on the opposing face, with the individual grounds commoned within wafers. There are two ground connections for every signal connection. For the receptacle wafers, both signal and ground spring beam contacts are contained within insert molded apertures, while the header wafers possess signal and ground contact blades captured within molded plastic. This basic layout and design information will become important as we understand the defects that require rework.

The original attach process for this connector utilizes vapor phase reflow, which is not widely used in the industry today. Vapor phase technology is well suited for this problem, and its merits are well documented.1,2 By boiling a liquid, energy is transferred through heat of condensation to the board and components. This method offers efficient heat transfer and is ideally suited for high mass component applications and reflow of solder independent of geometry and package density. With Pb-free solder’s need for higher temperatures to achieve melting points, vapor phase reflow is being touted as an attractive alternative due to its control of maximum temperature limited by the liquid’s boiling point.3

While vapor phase is ideally suited for initial attachment of this connector, a local vapor phase tool design offers an alternative for rework that “localizes” the process and limits thermal exposure to the board. This simplifies the manufacturing process by minimizing the removal of additional components surrounding the connector region.

During qualification of connector rework, we evaluated several methods to assess the quality and reliability of this interconnect solution. As noted, this application required increased bandwidth for leading-edge performance and scalability. This limited us to new surface mount technology, as opposed to through-hole soldered or press-fit connector attachment, which affect both density and signal integrity characteristics. While this supports the objectives of our product electrically, the plugging of processor nodes into the mid-plane can create mechanical stresses on the solder joints, even in the presence of additional guide and support features intended to protect the connector and solder joints during system actuation. During qualification of the rework process, we characterized solder joint integrity, intermetallic thickness and mechanical tolerance compliance to ensure that reworked connectors were capable of surviving these plugging stresses.

The number of leads, 5040, on the connector is extremely large compared to most surface mount connectors common in the industry. The large number of leads requires an excellent surface mount process yield. Table 1 has yield projections using a Poisson Distribution for 1, 2, 5, 10 and 25 ppm defects per lead, assuming one connector per board.4

Twenty-five ppm defects per lead is a good yield for surface mount leaded devices. In this case, the large connector yield is better. From this yield projection, it can be seen even in relatively low defect rates per lead that there will be enough natural fallout to where a rework process will be required.

The vapor phase reflow technology used is an off-the-shelf vapor phase rework machine that was adapted with special nozzles for this job. Internally, the machine is identified as a Local Vapor Phase (LVP) machine. It is important to note this rework process applies a localized area of hot vapor to achieve selective reflow of components on the assembly.

There are several steps to the large surface mount connector rework process:

Step 1. Before the assembly can undergo any solder reflow rework process, it must be baked. The bake operation removes any moisture absorbed by the assembly since the initial attach process. It is important to remove this moisture to avoid outgassing-induced damage to the board laminate material or moisture-sensitive components.

Step 2. After bake-out comes taping of areas that need thermal or physical protection, removal of temperature-sensitive components, and removal of components that interfere with the rework operation itself (Figure 2).

Step 3. The large surface mount connector is removed using an internally designed nozzle connector removal system that engages the connector and attaches to the LVP through hoses and mechanical connections. During removal, the connector and assembly are preheated with multiple sources of hot air and a heating strip, followed by full vapor phase reflow. At maximum reflow temperature, the LVP lifts the large surface mount connector from the PCB within the connector removal system nozzle. Then the PCB, apparatus and connector are cooled. The connector is disposed and the PCB is transferred to the site dress area (Figure 3).

Step 4. At site dress, the large surface mount connector site on the PCB is inspected for de-wet pads, excessively high solder bumps, PCB delamination and lifted SMT pads. Touch-up is performed on all de-wet pads with solder, flux and a solder iron. Pads that have excessive solder height or icicles are flattened using a solder iron and flux. Then the pads are cleaned with isopropyl alcohol (IPA), and a lint-free cloth. The PCB is transferred to a hot gas rework machine with a controlled z-height vacuum nozzle used for site redress (Figure 4).

Once the PCB reaches the target preheat temperature, the hot-gas rework tool will lower the site dress nozzle to the PCB, automatically sense the board surface, and set the vacuum for auto height adjustment. The site dress operation progresses slowly across the large connector SMT site. Once all the pads have been dressed, the pads are cleaned using IPA and lint-free cloth during the cooling cycle. Again, inspection is performed to examine the re-dressed SMT pads for lifted or damaged pads, damaged solder mask, excess solder or solder bridges. If solder bridges are found, they are removed using a solder iron and braided copper wick.

Step 5. The PCB is transferred to a semiautomatic screen printer adapted to permit selective site solder paste printing. The stencil has cut-outs to accommodate the remaining components on the PCB (Figure 5). Solder paste is applied to the stencil and printed on the site in a single blade pass. Then the PCB is removed from the screen printer and transferred to a solder paste measurement machine to verify the solder paste height and volume. After verification, solder paste deposits are visually reconfirmed under a microscope by an operator (Figure 6).

Step 6. The PCB is transferred back to the LVP and a new large surface mount connector attached to the PCB. An internal custom-designed attach nozzle system is used to engage the connector, PCB and LVP. Similar to the removal process, the connector and assembly are preheated with multiple sources of hot gas and a heating strip, followed by full vapor phase reflow and cool-down. Through the entire heating process, the connector and PCB area directly under the connector are clamped under a spring-load within the nozzle. This force is needed to balance between PCB flatness and connector lead coplanarity.

The PCB and newly attached large surface mount connector system are now ready for verification by various optical inspection, mechanical measurements, x-ray and electrical testing.

Inline Mechanical Verification Process
Due to the complexity and size of this connector, the team decided on certain critical mechanical measurements and verifications as controls for the rework process. The chosen measurements for the process included connector site PCB flatness, wafer-face to guide-block true positional alignment and mechanical verification test.5 These mechanical measurements and tests provide the ability to verify compliance with critical to function attributes of the connector for both qualification purposes, as well as quality monitoring in production.

Localized PCB flatness at the SMT site was determined to be a key contributor to reliability during stress testing of assemblies. Samples measured during initial rework were deemed acceptable; however, during the course of 2X rework, qualification samples were found outside of the optimum range. Therefore, inline measurement was implemented on all 2X reworks, with an automated measurement device to control site flatness prior to reattach of the connector. During the plugging process, it is extremely important that the mating interface of the connector meets certain dimensional criteria. Without meeting these criteria, the plugging process can result in damage to the PCB and mating connector.

Most critical of these measurements is verification of the wafer-face to guide block dimensions (Figure 7). The wafer-face to guide block test measures the z-dimension of the top and bottom of each wafer with respect to a plane created by the connector guide blocks; e.g., that is in front of or behind the plane created by the guide blocks. The connector guide blocks act as a hard stop during connector plugging.

If the wafer is above the specification limit, it will bottom out prior to guide block seating, resulting in an overstressed condition of the solder joints. If the wafer is under the specified dimension, it may not make good electrical contact with the mating wafer, resulting in electrical opens or intermittent connections.

Cross-section. As part of the process development and qualification effort, reworked cards were cross-sectioned at various process stages to ensure product integrity. The IBM East Fishkill Materials Lab established a cross-section protocol to ensure consistent, comparable, valid results were achieved. Sample preparation and cross-sectioning were performed with an aluminum stiffener bolted to the backside of the connector site to avoid procedure-induced artifacts through unintentional mechanical damage caused by handling. A quantifiable figure of merit protocol was created to enable comparison and tracking of the solder joint quality from varying rework processes. Boards were sectioned at connector removal, site redress, connector re-attach, and after exposure to various stress conditions. Cross-sectioning included evaluation of solder joint integrity, lead alignment, solder balls, contaminates, pad-lift and solder intermetallic integrity (Figure 8). As part of the site redress qualification, solder thickness was also measured to ensure proper solder coating thickness. This was necessary to avoid de-wet issues associated with oxidation of thin solder or exposed copper/tin intermetallics.

X-ray characterization. Reworked boards were inspected with 2D and 3D x-ray protocols to ensure product quality. A 2D x-ray auto-inspection algorithm was developed to detect solder defects and misaligned leads. The algorithm was tuned to ensure capture of significant defects, including low solder, non-wets and shorts. The program was tuned to minimize false calls, which require operator interpretation. 3D x-ray CT scan was performed on any questionable solder joints flagged by 2D inspection. For rework process qualification, full connectors were sampled with CT x-ray, regardless of 2D x-ray results.

Alternate qualification approach. Due to the nature of the defects and the manner in which they fail,  an alternate test approach was developed. The test methodology sequence was:

1. Mechanical verification at time zero.
2. Multiple connector plug cycles in the system configuration.
3. Mechanical verification.
4. Accelerated thermal cycling.

Accelerated thermal cycling (ATC) generally continued past the end of test until at least one solder joint had failed. By performing the thermal cycling and mechanical verification to detect the weak solder joints, it was possible to establish relative merit between the different rework methods.

Process selection activities began with samples from two different types of rework approaches. The first used the same basic tooling as the new build process, and the second used a localized heat rework tool. Table 2 summarizes the results of this initial evaluation.

Based on this limited sample size, the two approaches appeared equivalent, so the localized vapor phase heating rework method was selected as the process to put through qualification testing. This process provided greater flexibility and less overall risks to the total assembly than the new build reflow process. The process was optimized and then samples were submitted to the reliability evaluation (Table 3).


All samples passed initial system-level multi-plug preconditioning and accelerated thermal cycling. Testing was continued past the end of test until at least one part failed. These failures were deemed acceptable because when the acceleration factor of the test is taken into account, they failed late enough in testing to be considered end-of-life fails, and will occur at a much higher number of on/off cycles than systems will see in a lifetime. Therefore, it was concluded the localized rework process yielded parts exceeded all quality and reliability objectives (Table 3). 

Ed.: This article is adapted from a paper presented at the SMTA Pan Pac Symposium in January 2010, and is republished with permission.

We thank our coworkers, without whom this work would not have been possible. We wish to thank the IBM Fishkill Materials Analysis team for their analysis of the parts and our management who supported this effort.

1. N. Heilmann, “A Comparison of Vaporphase, Infrared, and Hotgas Soldering,” IEEE CH2629-4/88/0000-0070.
2. L. Livosky, A. Pietrikova and J. Durisin, “Monitoring of Temperature Profile of Vapour Phase Reflow Soldering,” IEEE 978-1-4244-3974-4/08, pp. 667-669.
3. A. Pietrikova, L. Livovsky, J. Urbancik, and R. Bucko, “Optimization of Lead Free Solders Reflow Profile,” IEEE 1-4244-0551-3/06, pp. 459-464.
4. P. Isaacs and K. Puttlitz, Chapter 20, “Area Array Component Replacement,” Area Array Interconnection Handbook, 2001, Kluwer Academic Publishers, pp. 804-837.
5. Mechanical verification test is an IBM internally developed test.

Jim Bielick, Brian Chapman, Mitchell Ferrill, Michael Fisher, Phil Isaacs, Eddie Kobeda and Theron Lewis are with IBM (;

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