In Case You Missed It
Published: 02 January 2009
by Staff
Component Integrity“Counterfeit Electronic Parts Detection through Packaging Evaluation”
Author: Kaushik Chatterjee
Abstract: Counterfeit electronic parts have become a significant cause of worry in the electronics supply chain. There are not many documented instances of illegal manufacturing for semiconductor parts. Most of the counterfeit parts detected in the electronics industry are either new or surplus parts or salvaged scrap parts. Packaging of these parts is altered to modify their identity. The modification can be as simple as removal of marking and remarking at one end, and recovery of die and repackaging at the other. All package modifications leave behind a trace, and here we present a systematic methodology for detecting signs of possible part modifications to determine the risk of a part or part lot being counterfeit. The evaluation methodology begins with visual inspection and marking permanency tests for external compliance, and x-ray inspection for internal compliance. These are followed by material evaluation in a destructive and nondestructive manner, such as XRF and material characterization for the mold compound. These processes are then followed by evaluation of the packages to identify defects degradations by failure mechanisms caused by the processes (e.g., cleaning, solder dipping of leads, reballing) used in creating counterfeit parts. This method of assessment is necessary since the electrical functionality and parameters may be met by the counterfeit parts, but their authenticity can only be evaluated by the packaging evaluation. The latent damages caused by the counterfeiting process only can be detected by packaging evaluation. We implement the package reliability and failure mechanism information in our detection method. We also provide recommendation on developing tamper-evident electronic packages that will create barriers to counterfeiting in the future. (IMAPS 2008, November 2008)
Packaging
“Thermosonic Gold to Gold Flip Chip Bonding for Small Die High Density Interconnect”
Author: Philip Couts
Abstract: The thermosonic flip-chip bonding profile consisting of temperature, load, ultrasonic power and time was investigated for small die attach. The study results show temperature changes impact the bonding lattice, which includes elastic modulus and tensile strength, resulting in different die shear strengths. In this study, heating was restricted to the bond tool tip to minimize temperature changes to the piezo transducer. Temperature changes will impact the impedance and dissipative ultrasonic energy of the piezo system. The study shows thermosonic flip-chip bonding parameters are influenced mutually. (IMAPS 2008, November 2008)
Solder Reliability
“Pb-Free Solder for Portable and High Temperature Electronic Devices”
Author: Ganesh Iyer
Abstract: This effort compares solder reliability between SAC 305 and SAC 105 for temperature cycling and drop test. Temperature cycling and drop test failure characteristics for an on-board package were determined experimentally. Data from these experiments were analyzed using two-parameter Weibull statistics and the characteristic lives from each set of experiments determined. The result of first failure and 50% failure for SAC 105 and SAC 305 is discussed. Site of failure and intermetallic thickness on the package side was investigated using the cross-sectioned samples. Also, dynamic simulation of temperature cycling and drop test was conducted to investigate the stress/strain induced in interconnects using ANSYS. Simulation using finite element model illustrated the temperature flow and stress distribution throughout the joint. The effect of accumulated stress per drop cycle and the hot spot is reported. The effect of the package integrity and weak joints with respect to drop reliability is also discussed. The results were interpreted and recommendations for the right Pb-free solder made for practical applications. (IMAPS 2008, November 2008)
“Reliability Testing of Ni-Modified Sncu And Sac 305 – Accelerated Thermal Cycling”
Authors: Joelle Arnold, Nathan Blattau, Craig Hillman and Keith Sweatman; jarnold@dfrsolutions.com.
Abstract: Interest in alternate Pb-free solder alloys has initiated a life prediction study of SN100C. This paper outlines the results of the thermal cycling portion of the testing and demonstrates that its robustness under accelerated life testing is somewhere between that of SnPb and SAC 305, with its performance dependent on the amount of strain to which it is subjected in the particular test. A low-cycle fatigue exponent of 2.38 is proposed, and the acceleration factor is presumed to be dependent on maximum temperature and is relatively insensitive to dwell time. (SMTA International, August 2008)
Circuits Assembly provides abstracts of papers from recent industry conferences and company white papers. With the amount of information increasing, our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.
