Design for Testability
Main considerations for incorporating test in a board design.
In our experience, there is a general lack of awareness about what needs to happen at the design level to increase the testability and overall test coverage of a finished assembly. This issue is straining the customer/supplier relationship, because it goes beyond what the supplier independently can provide without customer input and consideration during design.
What is the basic problem? Suppliers spend millions of dollars and countless labor hours on different quality initiatives aimed at producing zero defects. Yet none has been able to achieve this without one certain element: test!
In design for testability, the test method must be decided prior to finalization of the design. The four main options are functional, in-circuit (ICT) fixture, flying probe ICT, and boundary scan. Each has different design considerations.
ICT with fixtures has been around the longest and is the most widely used. It is particularly well suited for high-volume, low complexity designs, where the (high) cost of fixturing is justified by the volumes. It can test for shorts, opens, capacitance, resistance, inductance and more, depending on the level of test desired. It is fast and cheap (at a price per test level, once the fixture cost has been absorbed). But fixture costs are high and not suited to low volume. Also, test pad sizes must be large (0.030˝ to 0.040˝) and contained on every net of the design to give the fixture access to the board. The large size of the test pads makes this option difficult to incorporate onto high-density designs or designs with BGAs. After all, the main point of going to BGA package styles is to save real estate. Adding large test pads on every net defeats the purpose.
Functional test also is widely used to “exercise” the end functionality of the board. Its intent is to test circuit functionality and, in theory, catch most major defects, be they component-level or manufacturing defects. However, this is not an opens and shorts test. For example, it would not typically reveal wrong values for passives.
Functional fixturing can be tailored to almost any application. It detects problems with the board functionality or component-level failures, depending on the test hardware and software design. The custom design of test hardware and software, by its very nature, makes this option time-consuming and expensive. For many applications, especially quickturn prototypes or products with short time-to-market, this may not be practical. Also, it is likely functional test will not cover as much as 20% of the circuitry, and thus leave vulnerabilities in the finished product. This is why many high-volume, high-reliability customers do both ICT and functional.
Flying probe, like standard ICT, will test for shorts, opens, capacitance, resistance, inductance, etc. But rather than using fixed test probes, it uses robotic test heads. The obvious advantage is greater access to the circuit board, for greater test coverage, without the high cost of fixtures. In addition, it allows a more “forgiving” DfT approach by enabling smaller test pads (0.010˝ to 0.012˝), enabling use of unmasked vias as a test pad, and enabling test of SMT and PTH component leads. In essence, almost all standard SMT or mixed technology boards can now be tested and with relatively high coverage ratios, even though they may not have been designed with ICT in mind. Also, since there are no hard fixtures, the upfront costs are substantially less. It does require custom software test programming, at a typical one-time charge of $1,000 to $2,500, depending on the number of components on the board and the number of different line items on the BoM. The biggest drawback is test speed. It can take five to 60 minutes to test each board, depending on complexity. It definitely is more suited to low- to medium-volume applications. The other drawback is it cannot test BGA pins without specific test pads on the nets leading into the device, and it cannot functionally test ICs or catch cold solder joints.
Boundary scan is one of the most interesting, most powerful and least understood test options. Incorporated into the original design, it allows the user to program and test many of the major devices on the board, including memory and FPGAs. In essence, it allows programming and functional testing of all JTAG-compliant devices purely through software programming, with diagnostic-level reporting that permits fault isolation down to the pin level.
However, take into account during design that it requires a JTAG connector be added to the board, and that this connector be chained together with the JTAG-compliant devices.
It is the only practical option for testing BGAs because it does not require a test point on every net. It is relatively easy to generate the test programs, and thus relatively inexpensive, and comes with a one-time cost. It is fixtureless. It has powerful programming and diagnostic/debugging options both for engineering and manufacturing test departments. It gives the best of both worlds in terms of functional and ICT features.
Since BGA solder connections only can be examined through x-ray, this ability to test the BGA at the manufacturing level becomes critical. X-ray is inspection, not absolute validation. With these tools, the EMS firm can provide real-time feedback to the manufacturing floor to verify oven reflow profiles, all the more critical when processing BGAs. However, it is not capable of testing analog and passive devices.
The best test solution depends on the application and amount of money you are willing to spend. For high-reliability applications, the best solution may be a combination of these options.
Andrew Murrietta is CFO of Murrietta Circuits (murrietta.com); andy@murrietta.com. His column appears bimonthly.
