TimingDesigner 9.25 has enhanced Automerge functionality said to dramatically speed interface timing analysis. Permits use of reusable, model-based approach to timing analysis. Connects component timing models to create parameterized interface diagrams that can be used to validate timing and interactively test design alternatives. Interface models can be created early in the design phase to help drive constraint definition and timing budgeting. Propagation delay and signal integrity effects can be added for a more accurate representation of timing margins. Optional TimingDesigner Design Kit Library, for automated analysis process. Also updates Allegro PCB SI flow and features new design validation commands to identify critical margins, ensure proper analysis, and determine timing closure.

EMA Design Automation, www.timingdesigner.com/whatsnew

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