LYON, FRANCE – 3-D TSV wafers will be shipped in the millions and have the potential to impact as much as 25% of the memory business by 2015, says a new research report.
 
Excluding memory devices, Yole Developpement’s latest market forecast reveals 3-D TSV wafers could account for more than 6% of the total semiconductor industry by 2015.
 
Meanwhile, the equipment market for 3-D TSV manufacturing tools will rapidly expand to above $1 billion by 2013.
 
The research firm says consolidation is taking place in CMOS wafer fabs, with a shift toward a fabless foundry model.
 
A new infrastructure needs to be developed in the middle segment of the semiconductor industry supply chain, Yole says. New technologies, equipment and advanced materials coming from the front- and back-end worlds are being developed and will give rise to a revival of semiconductor packaging and circuit assembly.
 
The impetus for 3-D is clear and has not changed much since the technology was introduced into production for MEMS and CMOS image sensors; it is about achieving smaller form factor with increased package densities to meet bandwidth, RF, power consumption performance improvements and further cost reduction, says the firm. In addition, several players are driven by reliability motivations.
 
WL-CSP CMOS image sensors are poised to leave traditional edge interconnect configurations for “real” 3D-TSV architectures as soon as this year, Yole adds. Vias will be partially or completely filled. Additionally, the number of I/Os will expand to several hundreds of interconnects per chip, with a trend to stack the DSP chips under the image sensor chip itself.
 
MEMS will benefit from 3-D to combine MEMS with ASIC, while wireless SiPs will combine heterogeneous layers together. The market for 3-D stacked memories is imminent and is primarily driven by RAM-based memories; meanwhile, more Flash memory will be combined within MCP, PoP/SiP packages, cellphone card-slots and SSDs, according to the firm.
 
The question now is, Who will develop the lowest cost process and take the risk of the huge initial infrastructure investment required first? Going further, logic-based 3-D SOCs are to set to take off in the next two to three years for different applications. This “true” 3-D/IC integration will be achieved through the progressive segregation of several layers: 3-D partitioning of embedded memories, RF, analog and I/Os layers from the logic base chip will be achieved in the most cost-effective manner by reducing overall chip size areas, says Yole.
 
3-D WLP encapsulation is already in production in CMOS image sensors with via through the backside of the wafer. It will expand to power amplifier modules as well, says the firm.
 
If via-last will account for a large portion of the market, Yole sees a clear trend toward via-first configurations and smaller via sizes approaching 1-5 µm diameters with 500 to 2000 interconnects per chip.
 
3-D interposer module is already in small production for several MEMS applications to combine ASIC and MEMS chips together in a true WLP approach. This technology platform is likely to expand rapidly into many SiP application spaces, says the firm.
 
Several barriers to entry exist for full-scale 3-D IC integration, including test, 3-D EDA design tools, thermal management and 300 mm equipment availability. As contact probe test technologies tend to be more limited with via pad density increasing, they may not scale to future pad dimension pitch shrinks. Moreover, as one portion of the industry is going toward wafer-to-wafer stacking schemes with thin wafers, new requirements are emerging for testing without damage at the wafer level to ensure the electrical functionality of the TSV, RDL and Bump pad structures prior to the stacking of each layer. As a consequence of this, many companies are requesting contact-less testing technologies, says Yole. Technology and equipment are being developed for wafer surface inspection, open/shorts electrical testing and 3-D system level functionality validation.
 
The landscape is different regarding the availability of 3-D EDA design and thermal management software tools. Yole sees effort in this area; however, the company believes it will be a challenge for the industry to get the tools ready by 2011.
 
The availability of 300 mm 3-D TSV equipment is a question of time, the company says. First 300 mm tool clusters have been shipped this year for production pilot lines.  

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