ALBANY, NY – Sematech, the Semiconductor Industry Association and Semiconductor Research Corp. said they have established a 3D enablement program to drive industry standardization efforts and technical specifications for heterogeneous 3D integration. 

Administered by Sematech’s 3D interconnect program, the effort aims to establish the infrastructure necessary for the industry to leverage 3D packaging technology for innovative new applications.

The program will focus primarily on developing technologies and specifications necessary for establishing standards in critical areas such as inspection, metrology, microbumping, bonding and thin wafer and die handling. Sematech will partner with SRC to enable select university research projects.

First efforts will focus on developing necessary standards and technical specifications, followed by planning activities to identify key areas for developing design tools to support 3D chip design. 

The 3D enablement program is open to international fabless, fab-lite and IDM companies, outsourced assembly and test suppliers, and tool vendors.

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