BANNOCKBURN, IL – The updated IPC/JEDEC-9704A, Printed Circuit Assembly Strain Gage Test Guideline, makes it easier for engineers to run strain gage tests during the manufacturing process, says IPC.

“Revision A is about making sure there’s a common accepted practice for measuring manufacturing strain on printed board assemblies due to board flexure,” said Jagadeesh Radhakrishnan, a reliability engineer with Intel and leader of the effort within the IPC SMT Attachment Reliability Test Methods Task Group that helped revise the guideline. Whereas the first-generation document provided industry with target pass/fail points, the A revision, “… changes the focus to providing a methodology. It doesn’t give you targets; it thoroughly explains how to measure strain.”

Revision A includes formulas for calculating strain and describes techniques for analyzing data derived from these tests. The tests can be performed at many stages during the manufacturing of printed board assemblies. Components can be tested during assembly or during test processes in the factory or just before they’re packaged.

IPC/JEDEC-9704A also provides recommendations for sockets and ceramic capacitors; in the past, it just addressed ball grid arrays. “It also changes parameters for in-circuit test fixtures, providing best design practices so users will have fewer issues,” said Radhakrishnan.

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