LAS VEGAS – The 35th annual EOS/ESD Symposium will be held Sept. 8-13 at the Rio All Suites Hotel here.

The symposium provides an overview of the latest progress in electrical overstress and electrostatic discharge protection technology. It includes tutorials, technical presentations, exhibits of ESD control products and services, and workshops.

Highlights include 40 tutorials, including An Overview of Integrated Circuit ESD: ESD Threat, Testing, Design Concepts, & Debugging; ESD Design in HV Technologies; Waveforms and the Safe Handling of Devices; Contamination & ESD Issues in Flat Panel Display Manufacturing Process, and Costly Controversial ESD Myths.

Technical Sessions include On-Chip Protection in Emerging CMOS Technologies, Design for CMOS, Protection for High Voltage Applications; Analysis of Factory Processes, Properties of Materials; ESD Device Physics, System-Level Design, Electronic Design Automation, System-Level Characterization Cases, RF and High Voltage Design, and Transient Test Techniques and Modeling of ESD Testers.

The symposium has two “Year in Review” sessions on factory and device standards.

Workshops include Effective Strategies for ESD Design Team Organization and SoC Support; HBM and CDM Correlation to Field Returns and Manufacturing Rejects; System Level ESD Protection – On-Chip or On-Board?; Transient Latch-up; EOS Mitigation – What is the Best Strategy to Get Rid of EOS Failures, and 3D/TSV.

Visit www.esda.org/symposiaEOS-ESD for more information.

Register at www.esda.org/onlineregistrations.

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