RICHARDSON, TX – An eBook on how to test DDR memory with non-intrusive JTAG or boundary-scan methods is available.

A recent survey of engineers by iNEMI found testing memory soldered to circuit boards is a problem for system manufacturers, according to Asset InterTech, the book’s publisher.

“The ability to thoroughly test, characterize and diagnose problems with soldered-down memory is one of the most pressing problems in the industry,” said author Kent Zetterberg, product manager, Asset InterTech. “Because DDR3 memory chips have become so prevalent in high-speed systems, I used this technology as the basis for explaining how JTAG or boundary-scan methods can be integrated into every step of a system’s lifecycle, beginning in design and transitioning into manufacturing and field service.”

Testing DDR3 Memory with Boundary Scan / JTAG is available at: http://www.asset-intertech.com/Products/Boundary-Scan-Test/BST-Software/Testing_DDR3_memory_Boundary_Scan-JTAG.

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