AUSTIN, TX -- Major DRAM makers Micron, SK Hynix, and Samsung have announced versions of stacked memory with through silicon vias (TSVs) for high-performance applications.

Some CMOS image sensors are also in production with die stacking and TSVs. The remaining question is what is holding back the expansion of 3D IC in other applications?

Market research firm TechSearch International addresses this in its just-published report, "3D IC Gap Analysis: Remaining Issues, Solutions, Market Status." The 135-page report provides insight into the remaining technical gaps and business issues holding back the expansion of 3D ICs. Potential solutions from various research organizations and companies are highlighted.

While great progress has been made in via formation and filling, process steps such as debonding during wafer thinning remain problematic. Improvements in process yield that lower cost are necessary if the technology is to expand into new applications. Progress has been made in design tools and methodology, but additional work is required. Low-power design of 3D IC stacks remains in the early stages. Cost-effective thermal solutions are still required for
memory/logic and logic/logic stacks. Progress in the testing area has been reported, but work is still needed. Clarity on the issue of responsibility for the assembly and logistics requires resolution. Cost/performance targets must be met, relative to available alternatives.

This report examines challenges in adopting the technology today and a timeframe for high-volume manufacturing with details of each application and its requirements and provides "realistic" market forecasts. 

• Prev
• Next