WASHINGTON -- By challenging the technology community to integrate the collective functions hosted by an entire PCB onto a device approaching the size of a single chip, DARPA’s newest program is making a bid to usher in a fresh dimension of technology miniaturization.

“We are trying to push the massive amount of integration you typically get on a printed circuit board down into an even more compact format,” said Dr. Daniel Green, manager of the new program, whose acronym, “CHIPS,” is itself a typographic feat of miniaturization; the program’s full name is the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies Program. “It’s not just a fun acronym,” Green said. “The program is all about devising a physical library of component chips, or chiplets, that we can assemble in a modular fashion.”

A primary driver of CHIPS is to develop a novel, industry-friendly architectural strategy for designing and building new generations of microsystems in which the time and energy it takes to move signals—that is, data—between chips is reduced by factors of tens or even hundreds. “This is increasingly important for the data-intensive processing that we have to do as the data sets we are dealing with get bigger and bigger,” Green said. Although the program does not specify applications, the new architectural strategy at the program’s heart could open new routes to computational efficiencies required for such feats as identifying objects and actions in real-time video feeds, real-time language translation, and coordinating motion on-the-fly among swarms of fast-moving unmanned aerial vehicles (UAVs).

DARPA has posted a Request for Information (RFI), designated on fbo.gov as DARPA-SN-16-50, to harvest ideas at the front-end of the program from expert and industry players so that the CHIPS team can hone the details of the program in ways that would facilitate graceful incorporation of these new approaches within existing commercial semiconductor foundries and electronics fabrication facilities. “Key to the success of CHIPS will be standards and interfaces, and this means we will be working with a community, not all by ourselves,” said Green. The CHIPS team expects to use input from the RFI and a workshop anticipated to occur later this summer to prepare a Broad Agency Announcement (BAA). The BAA, which will also be posted on fbo.gov, will specify the program’s technical goals and how potential performers can submit proposals.

A major aspect of the CHIPS vision is the eventual availability of a library of custom and commercial “chiplets”—small-scale chips that individually embody a particular function, such as data storage, computation, signal processing, and managing the form and flow of data. By assembling and integrating dozens of chiplets, mosaic style, on an interposer, which is like a printed circuit board writ small, all of those microsystems’ functions could be performed in a much closer huddle and can perform more efficiently than if they were distributed in the usual way among a suite of chips attached to a conventional PCB.

Another big win Green hopes to score with the modular architecture championed by the CHIPS program is the ability to separate out onto individual chiplets the many IP blocks developed for and aggregated into commercial monolithic chips. Such partitioning of computational functions could open the way for the DoD to negotiate more affordable licensing of smaller and more specific IP blocks suitable for repurposing for particular technologies and systems. “If CHIPS is successful, we will gain access to a wider variety of specialized IP blocks that we will be able to integrate into our systems more easily and with lower costs,” said Green. “This should be a win for both the commercial and defense sectors.”

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