SAN JOSE, CA – The 16th annual International Wafer-Level Packaging Conference will be held here Oct. 22-24.

The technical sessions are organized into three tracks: wafer-level packaging, 3D packaging, and advanced manufacturing and test. The wafer-level packaging track features sessions on materials, reliability, metrology, processing, and new technology, such as fan-out WLP.

The 3D packaging track features sessions on design, test, characterization, wafer bonding, chip stacking, and processing for fan-out.

The advanced manufacturing and test track features sessions on process materials, equipment, inspection, and more.

Packaging technology experts John Lau, PhD, Unimicron Technology; John Hunt, ASE (US); Gilad Sharon, PhD, ANSYS and Jeff Gotro, PhD, InnoCentrix, are scheduled to lead half-day workshops on Oct. 24.

For more information, visit www.iwlpc.com.

Register now for PCB West, the leading conference and exhibition for printed circuit board design! Coming Sept. 9-12 to the Santa Clara Convention Center. pcbwest.com

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