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SEOUL – Samsung Electronics has developed the industry’s first 12-layer 3D-TSV (through silicon via) technology, according to reports.

This packaging technology requires pinpoint accuracy to vertically interconnect 12 DRAM chips through a 3-D configuration of more than 60,000 TSV holes, each 1/20 the thickness of a human hair. The thickness (720µm) is the same as the current 8-layer high bandwidth memory-2 (HBM2) products.

The technology features a shorter data transmission time between chips than current wire bonding technology.

“Packaging technology that secures all of the intricacies of ultra-performance memory is becoming tremendously important, with the wide variety of new-age applications, such as artificial intelligence and high-power computing,” said Hong-Joo Baek, executive vice president of Test and System Package at Samsung Electronics.

“As Moore’s law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical. We want to be at the forefront of this state-of-the-art chip packaging technology.”

Samsung will soon be able to mass produce 24-GB high bandwidth memory.

 

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