MORRISVILLE, NC – iNEMI issued a call for participation for its first level interconnect void characterization project. Two webinar sessions will be held Dec. 12.

This project will study voids in flip-chip interconnect to determine their location and volume. It will also seek to understand how voiding in first level interconnect affects product reliability and what level of voiding is acceptable while maintaining reliability requirements.

The project will have two phases: determine recommended inspection capabilities for micro-voids in first level interconnect materials; determine the relationship between voids and the electrical and mechanical reliability of the assembly.

The project is expected to develop technical guidelines regarding acceptable voiding characteristics for flip-chip interconnects that can be shared with industry and relevant standards bodies.

The project is led by Lee Kor Oon (Intel) as project leader, with Sze Pei Lim (Indium) and Kiyoshi Ooi (Shinko) as co-leaders.

For more information, visit https://tinyurl.com/tv89qfx.

To register for session 1 (APAC), visit https://tinyurl.com/vz4f792.

To register for session 2 (Americas and EMEA), visit https://tinyurl.com/twhhyvn.

• Prev
• Next